diff options
| author | Yijing Wang <wangyijing@huawei.com> | 2015-05-21 15:05:04 +0800 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2015-05-29 15:35:26 -0500 |
| commit | 777e61ea40e4a94081b3123c76ea3fe977c368a2 (patch) | |
| tree | 69f6230aa9f5a8213f3bd0445d6c33251c906aec /drivers/pci/pcie | |
| parent | c8fc9339409df88693742d323819ab8415cd2e9d (diff) | |
PCI: Use dev->has_secondary_link to find downstream PCIe links
Previously we assumed that PCIe Root Ports and Downstream Ports had Links
on their secondary side. That is true in most systems, but it is possible
to connect a switch with either an Upstream or a Downstream Port leading
downstream.
Instead of relying on the component type to identify devices that have
links leading downstream, use the "dev->has_secondary_link" field.
[bhelgaas: changelog]
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/pci/pcie')
| -rw-r--r-- | drivers/pci/pcie/aer/aerdrv_core.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/pci/pcie/aer/aerdrv_core.c b/drivers/pci/pcie/aer/aerdrv_core.c index 5653ea94547f..9803e3d039fe 100644 --- a/drivers/pci/pcie/aer/aerdrv_core.c +++ b/drivers/pci/pcie/aer/aerdrv_core.c @@ -425,8 +425,7 @@ static pci_ers_result_t reset_link(struct pci_dev *dev) if (driver && driver->reset_link) { status = driver->reset_link(udev); - } else if (pci_pcie_type(udev) == PCI_EXP_TYPE_DOWNSTREAM || - pci_pcie_type(udev) == PCI_EXP_TYPE_ROOT_PORT) { + } else if (udev->has_secondary_link) { status = default_reset_link(udev); } else { dev_printk(KERN_DEBUG, &dev->dev, |