diff options
author | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 15:20:36 -0700 |
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committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 15:20:36 -0700 |
commit | 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch) | |
tree | 0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/net/wan/dscc4.c |
Linux-2.6.12-rc2
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
Diffstat (limited to 'drivers/net/wan/dscc4.c')
-rw-r--r-- | drivers/net/wan/dscc4.c | 2074 |
1 files changed, 2074 insertions, 0 deletions
diff --git a/drivers/net/wan/dscc4.c b/drivers/net/wan/dscc4.c new file mode 100644 index 000000000000..520a77a798e2 --- /dev/null +++ b/drivers/net/wan/dscc4.c @@ -0,0 +1,2074 @@ +/* + * drivers/net/wan/dscc4/dscc4.c: a DSCC4 HDLC driver for Linux + * + * This software may be used and distributed according to the terms of the + * GNU General Public License. + * + * The author may be reached as romieu@cogenit.fr. + * Specific bug reports/asian food will be welcome. + * + * Special thanks to the nice people at CS-Telecom for the hardware and the + * access to the test/measure tools. + * + * + * Theory of Operation + * + * I. Board Compatibility + * + * This device driver is designed for the Siemens PEB20534 4 ports serial + * controller as found on Etinc PCISYNC cards. The documentation for the + * chipset is available at http://www.infineon.com: + * - Data Sheet "DSCC4, DMA Supported Serial Communication Controller with + * 4 Channels, PEB 20534 Version 2.1, PEF 20534 Version 2.1"; + * - Application Hint "Management of DSCC4 on-chip FIFO resources". + * - Errata sheet DS5 (courtesy of Michael Skerritt). + * Jens David has built an adapter based on the same chipset. Take a look + * at http://www.afthd.tu-darmstadt.de/~dg1kjd/pciscc4 for a specific + * driver. + * Sample code (2 revisions) is available at Infineon. + * + * II. Board-specific settings + * + * Pcisync can transmit some clock signal to the outside world on the + * *first two* ports provided you put a quartz and a line driver on it and + * remove the jumpers. The operation is described on Etinc web site. If you + * go DCE on these ports, don't forget to use an adequate cable. + * + * Sharing of the PCI interrupt line for this board is possible. + * + * III. Driver operation + * + * The rx/tx operations are based on a linked list of descriptors. The driver + * doesn't use HOLD mode any more. HOLD mode is definitely buggy and the more + * I tried to fix it, the more it started to look like (convoluted) software + * mutation of LxDA method. Errata sheet DS5 suggests to use LxDA: consider + * this a rfc2119 MUST. + * + * Tx direction + * When the tx ring is full, the xmit routine issues a call to netdev_stop. + * The device is supposed to be enabled again during an ALLS irq (we could + * use HI but as it's easy to lose events, it's fscked). + * + * Rx direction + * The received frames aren't supposed to span over multiple receiving areas. + * I may implement it some day but it isn't the highest ranked item. + * + * IV. Notes + * The current error (XDU, RFO) recovery code is untested. + * So far, RDO takes his RX channel down and the right sequence to enable it + * again is still a mistery. If RDO happens, plan a reboot. More details + * in the code (NB: as this happens, TX still works). + * Don't mess the cables during operation, especially on DTE ports. I don't + * suggest it for DCE either but at least one can get some messages instead + * of a complete instant freeze. + * Tests are done on Rev. 20 of the silicium. The RDO handling changes with + * the documentation/chipset releases. + * + * TODO: + * - test X25. + * - use polling at high irq/s, + * - performance analysis, + * - endianness. + * + * 2001/12/10 Daniela Squassoni <daniela@cyclades.com> + * - Contribution to support the new generic HDLC layer. + * + * 2002/01 Ueimor + * - old style interface removal + * - dscc4_release_ring fix (related to DMA mapping) + * - hard_start_xmit fix (hint: TxSizeMax) + * - misc crapectomy. + */ + +#include <linux/module.h> +#include <linux/types.h> +#include <linux/errno.h> +#include <linux/list.h> +#include <linux/ioport.h> +#include <linux/pci.h> +#include <linux/kernel.h> +#include <linux/mm.h> + +#include <asm/system.h> +#include <asm/cache.h> +#include <asm/byteorder.h> +#include <asm/uaccess.h> +#include <asm/io.h> +#include <asm/irq.h> + +#include <linux/init.h> +#include <linux/string.h> + +#include <linux/if_arp.h> +#include <linux/netdevice.h> +#include <linux/skbuff.h> +#include <linux/delay.h> +#include <net/syncppp.h> +#include <linux/hdlc.h> + +/* Version */ +static const char version[] = "$Id: dscc4.c,v 1.173 2003/09/20 23:55:34 romieu Exp $ for Linux\n"; +static int debug; +static int quartz; + +#ifdef CONFIG_DSCC4_PCI_RST +static DECLARE_MUTEX(dscc4_sem); +static u32 dscc4_pci_config_store[16]; +#endif + +#define DRV_NAME "dscc4" + +#undef DSCC4_POLLING + +/* Module parameters */ + +MODULE_AUTHOR("Maintainer: Francois Romieu <romieu@cogenit.fr>"); +MODULE_DESCRIPTION("Siemens PEB20534 PCI Controler"); +MODULE_LICENSE("GPL"); +module_param(debug, int, 0); +MODULE_PARM_DESC(debug,"Enable/disable extra messages"); +module_param(quartz, int, 0); +MODULE_PARM_DESC(quartz,"If present, on-board quartz frequency (Hz)"); + +/* Structures */ + +struct thingie { + int define; + u32 bits; +}; + +struct TxFD { + u32 state; + u32 next; + u32 data; + u32 complete; + u32 jiffies; /* Allows sizeof(TxFD) == sizeof(RxFD) + extra hack */ +}; + +struct RxFD { + u32 state1; + u32 next; + u32 data; + u32 state2; + u32 end; +}; + +#define DUMMY_SKB_SIZE 64 +#define TX_LOW 8 +#define TX_RING_SIZE 32 +#define RX_RING_SIZE 32 +#define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct TxFD) +#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct RxFD) +#define IRQ_RING_SIZE 64 /* Keep it a multiple of 32 */ +#define TX_TIMEOUT (HZ/10) +#define DSCC4_HZ_MAX 33000000 +#define BRR_DIVIDER_MAX 64*0x00004000 /* Cf errata DS5 p.10 */ +#define dev_per_card 4 +#define SCC_REGISTERS_MAX 23 /* Cf errata DS5 p.4 */ + +#define SOURCE_ID(flags) (((flags) >> 28) & 0x03) +#define TO_SIZE(state) (((state) >> 16) & 0x1fff) + +/* + * Given the operating range of Linux HDLC, the 2 defines below could be + * made simpler. However they are a fine reminder for the limitations of + * the driver: it's better to stay < TxSizeMax and < RxSizeMax. + */ +#define TO_STATE_TX(len) cpu_to_le32(((len) & TxSizeMax) << 16) +#define TO_STATE_RX(len) cpu_to_le32((RX_MAX(len) % RxSizeMax) << 16) +#define RX_MAX(len) ((((len) >> 5) + 1) << 5) /* Cf RLCR */ +#define SCC_REG_START(dpriv) (SCC_START+(dpriv->dev_id)*SCC_OFFSET) + +struct dscc4_pci_priv { + u32 *iqcfg; + int cfg_cur; + spinlock_t lock; + struct pci_dev *pdev; + + struct dscc4_dev_priv *root; + dma_addr_t iqcfg_dma; + u32 xtal_hz; +}; + +struct dscc4_dev_priv { + struct sk_buff *rx_skbuff[RX_RING_SIZE]; + struct sk_buff *tx_skbuff[TX_RING_SIZE]; + + struct RxFD *rx_fd; + struct TxFD *tx_fd; + u32 *iqrx; + u32 *iqtx; + + /* FIXME: check all the volatile are required */ + volatile u32 tx_current; + u32 rx_current; + u32 iqtx_current; + u32 iqrx_current; + + volatile u32 tx_dirty; + volatile u32 ltda; + u32 rx_dirty; + u32 lrda; + + dma_addr_t tx_fd_dma; + dma_addr_t rx_fd_dma; + dma_addr_t iqtx_dma; + dma_addr_t iqrx_dma; + + u32 scc_regs[SCC_REGISTERS_MAX]; /* Cf errata DS5 p.4 */ + + struct timer_list timer; + + struct dscc4_pci_priv *pci_priv; + spinlock_t lock; + + int dev_id; + volatile u32 flags; + u32 timer_help; + + unsigned short encoding; + unsigned short parity; + struct net_device *dev; + sync_serial_settings settings; + void __iomem *base_addr; + u32 __pad __attribute__ ((aligned (4))); +}; + +/* GLOBAL registers definitions */ +#define GCMDR 0x00 +#define GSTAR 0x04 +#define GMODE 0x08 +#define IQLENR0 0x0C +#define IQLENR1 0x10 +#define IQRX0 0x14 +#define IQTX0 0x24 +#define IQCFG 0x3c +#define FIFOCR1 0x44 +#define FIFOCR2 0x48 +#define FIFOCR3 0x4c +#define FIFOCR4 0x34 +#define CH0CFG 0x50 +#define CH0BRDA 0x54 +#define CH0BTDA 0x58 +#define CH0FRDA 0x98 +#define CH0FTDA 0xb0 +#define CH0LRDA 0xc8 +#define CH0LTDA 0xe0 + +/* SCC registers definitions */ +#define SCC_START 0x0100 +#define SCC_OFFSET 0x80 +#define CMDR 0x00 +#define STAR 0x04 +#define CCR0 0x08 +#define CCR1 0x0c +#define CCR2 0x10 +#define BRR 0x2C +#define RLCR 0x40 +#define IMR 0x54 +#define ISR 0x58 + +#define GPDIR 0x0400 +#define GPDATA 0x0404 +#define GPIM 0x0408 + +/* Bit masks */ +#define EncodingMask 0x00700000 +#define CrcMask 0x00000003 + +#define IntRxScc0 0x10000000 +#define IntTxScc0 0x01000000 + +#define TxPollCmd 0x00000400 +#define RxActivate 0x08000000 +#define MTFi 0x04000000 +#define Rdr 0x00400000 +#define Rdt 0x00200000 +#define Idr 0x00100000 +#define Idt 0x00080000 +#define TxSccRes 0x01000000 +#define RxSccRes 0x00010000 +#define TxSizeMax 0x1fff /* Datasheet DS1 - 11.1.1.1 */ +#define RxSizeMax 0x1ffc /* Datasheet DS1 - 11.1.2.1 */ + +#define Ccr0ClockMask 0x0000003f +#define Ccr1LoopMask 0x00000200 +#define IsrMask 0x000fffff +#define BrrExpMask 0x00000f00 +#define BrrMultMask 0x0000003f +#define EncodingMask 0x00700000 +#define Hold 0x40000000 +#define SccBusy 0x10000000 +#define PowerUp 0x80000000 +#define Vis 0x00001000 +#define FrameOk (FrameVfr | FrameCrc) +#define FrameVfr 0x80 +#define FrameRdo 0x40 +#define FrameCrc 0x20 +#define FrameRab 0x10 +#define FrameAborted 0x00000200 +#define FrameEnd 0x80000000 +#define DataComplete 0x40000000 +#define LengthCheck 0x00008000 +#define SccEvt 0x02000000 +#define NoAck 0x00000200 +#define Action 0x00000001 +#define HiDesc 0x20000000 + +/* SCC events */ +#define RxEvt 0xf0000000 +#define TxEvt 0x0f000000 +#define Alls 0x00040000 +#define Xdu 0x00010000 +#define Cts 0x00004000 +#define Xmr 0x00002000 +#define Xpr 0x00001000 +#define Rdo 0x00000080 +#define Rfs 0x00000040 +#define Cd 0x00000004 +#define Rfo 0x00000002 +#define Flex 0x00000001 + +/* DMA core events */ +#define Cfg 0x00200000 +#define Hi 0x00040000 +#define Fi 0x00020000 +#define Err 0x00010000 +#define Arf 0x00000002 +#define ArAck 0x00000001 + +/* State flags */ +#define Ready 0x00000000 +#define NeedIDR 0x00000001 +#define NeedIDT 0x00000002 +#define RdoSet 0x00000004 +#define FakeReset 0x00000008 + +/* Don't mask RDO. Ever. */ +#ifdef DSCC4_POLLING +#define EventsMask 0xfffeef7f +#else +#define EventsMask 0xfffa8f7a +#endif + +/* Functions prototypes */ +static void dscc4_rx_irq(struct dscc4_pci_priv *, struct dscc4_dev_priv *); +static void dscc4_tx_irq(struct dscc4_pci_priv *, struct dscc4_dev_priv *); +static int dscc4_found1(struct pci_dev *, void __iomem *ioaddr); +static int dscc4_init_one(struct pci_dev *, const struct pci_device_id *ent); +static int dscc4_open(struct net_device *); +static int dscc4_start_xmit(struct sk_buff *, struct net_device *); +static int dscc4_close(struct net_device *); +static int dscc4_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); +static int dscc4_init_ring(struct net_device *); +static void dscc4_release_ring(struct dscc4_dev_priv *); +static void dscc4_timer(unsigned long); +static void dscc4_tx_timeout(struct net_device *); +static irqreturn_t dscc4_irq(int irq, void *dev_id, struct pt_regs *ptregs); +static int dscc4_hdlc_attach(struct net_device *, unsigned short, unsigned short); +static int dscc4_set_iface(struct dscc4_dev_priv *, struct net_device *); +#ifdef DSCC4_POLLING +static int dscc4_tx_poll(struct dscc4_dev_priv *, struct net_device *); +#endif + +static inline struct dscc4_dev_priv *dscc4_priv(struct net_device *dev) +{ + return dev_to_hdlc(dev)->priv; +} + +static inline struct net_device *dscc4_to_dev(struct dscc4_dev_priv *p) +{ + return p->dev; +} + +static void scc_patchl(u32 mask, u32 value, struct dscc4_dev_priv *dpriv, + struct net_device *dev, int offset) +{ + u32 state; + + /* Cf scc_writel for concern regarding thread-safety */ + state = dpriv->scc_regs[offset >> 2]; + state &= ~mask; + state |= value; + dpriv->scc_regs[offset >> 2] = state; + writel(state, dpriv->base_addr + SCC_REG_START(dpriv) + offset); +} + +static void scc_writel(u32 bits, struct dscc4_dev_priv *dpriv, + struct net_device *dev, int offset) +{ + /* + * Thread-UNsafe. + * As of 2002/02/16, there are no thread racing for access. + */ + dpriv->scc_regs[offset >> 2] = bits; + writel(bits, dpriv->base_addr + SCC_REG_START(dpriv) + offset); +} + +static inline u32 scc_readl(struct dscc4_dev_priv *dpriv, int offset) +{ + return dpriv->scc_regs[offset >> 2]; +} + +static u32 scc_readl_star(struct dscc4_dev_priv *dpriv, struct net_device *dev) +{ + /* Cf errata DS5 p.4 */ + readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR); + return readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR); +} + +static inline void dscc4_do_tx(struct dscc4_dev_priv *dpriv, + struct net_device *dev) +{ + dpriv->ltda = dpriv->tx_fd_dma + + ((dpriv->tx_current-1)%TX_RING_SIZE)*sizeof(struct TxFD); + writel(dpriv->ltda, dpriv->base_addr + CH0LTDA + dpriv->dev_id*4); + /* Flush posted writes *NOW* */ + readl(dpriv->base_addr + CH0LTDA + dpriv->dev_id*4); +} + +static inline void dscc4_rx_update(struct dscc4_dev_priv *dpriv, + struct net_device *dev) +{ + dpriv->lrda = dpriv->rx_fd_dma + + ((dpriv->rx_dirty - 1)%RX_RING_SIZE)*sizeof(struct RxFD); + writel(dpriv->lrda, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4); +} + +static inline unsigned int dscc4_tx_done(struct dscc4_dev_priv *dpriv) +{ + return dpriv->tx_current == dpriv->tx_dirty; +} + +static inline unsigned int dscc4_tx_quiescent(struct dscc4_dev_priv *dpriv, + struct net_device *dev) +{ + return readl(dpriv->base_addr + CH0FTDA + dpriv->dev_id*4) == dpriv->ltda; +} + +int state_check(u32 state, struct dscc4_dev_priv *dpriv, struct net_device *dev, + const char *msg) +{ + int ret = 0; + + if (debug > 1) { + if (SOURCE_ID(state) != dpriv->dev_id) { + printk(KERN_DEBUG "%s (%s): Source Id=%d, state=%08x\n", + dev->name, msg, SOURCE_ID(state), state ); + ret = -1; + } + if (state & 0x0df80c00) { + printk(KERN_DEBUG "%s (%s): state=%08x (UFO alert)\n", + dev->name, msg, state); + ret = -1; + } + } + return ret; +} + +void dscc4_tx_print(struct net_device *dev, struct dscc4_dev_priv *dpriv, + char *msg) +{ + printk(KERN_DEBUG "%s: tx_current=%02d tx_dirty=%02d (%s)\n", + dev->name, dpriv->tx_current, dpriv->tx_dirty, msg); +} + +static void dscc4_release_ring(struct dscc4_dev_priv *dpriv) +{ + struct pci_dev *pdev = dpriv->pci_priv->pdev; + struct TxFD *tx_fd = dpriv->tx_fd; + struct RxFD *rx_fd = dpriv->rx_fd; + struct sk_buff **skbuff; + int i; + + pci_free_consistent(pdev, TX_TOTAL_SIZE, tx_fd, dpriv->tx_fd_dma); + pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma); + + skbuff = dpriv->tx_skbuff; + for (i = 0; i < TX_RING_SIZE; i++) { + if (*skbuff) { + pci_unmap_single(pdev, tx_fd->data, (*skbuff)->len, + PCI_DMA_TODEVICE); + dev_kfree_skb(*skbuff); + } + skbuff++; + tx_fd++; + } + + skbuff = dpriv->rx_skbuff; + for (i = 0; i < RX_RING_SIZE; i++) { + if (*skbuff) { + pci_unmap_single(pdev, rx_fd->data, + RX_MAX(HDLC_MAX_MRU), PCI_DMA_FROMDEVICE); + dev_kfree_skb(*skbuff); + } + skbuff++; + rx_fd++; + } +} + +inline int try_get_rx_skb(struct dscc4_dev_priv *dpriv, struct net_device *dev) +{ + unsigned int dirty = dpriv->rx_dirty%RX_RING_SIZE; + struct RxFD *rx_fd = dpriv->rx_fd + dirty; + const int len = RX_MAX(HDLC_MAX_MRU); + struct sk_buff *skb; + int ret = 0; + + skb = dev_alloc_skb(len); + dpriv->rx_skbuff[dirty] = skb; + if (skb) { + skb->protocol = hdlc_type_trans(skb, dev); + rx_fd->data = pci_map_single(dpriv->pci_priv->pdev, skb->data, + len, PCI_DMA_FROMDEVICE); + } else { + rx_fd->data = (u32) NULL; + ret = -1; + } + return ret; +} + +/* + * IRQ/thread/whatever safe + */ +static int dscc4_wait_ack_cec(struct dscc4_dev_priv *dpriv, + struct net_device *dev, char *msg) +{ + s8 i = 0; + + do { + if (!(scc_readl_star(dpriv, dev) & SccBusy)) { + printk(KERN_DEBUG "%s: %s ack (%d try)\n", dev->name, + msg, i); + goto done; + } + set_current_state(TASK_UNINTERRUPTIBLE); + schedule_timeout(10); + rmb(); + } while (++i > 0); + printk(KERN_ERR "%s: %s timeout\n", dev->name, msg); +done: + return (i >= 0) ? i : -EAGAIN; +} + +static int dscc4_do_action(struct net_device *dev, char *msg) +{ + void __iomem *ioaddr = dscc4_priv(dev)->base_addr; + s16 i = 0; + + writel(Action, ioaddr + GCMDR); + ioaddr += GSTAR; + do { + u32 state = readl(ioaddr); + + if (state & ArAck) { + printk(KERN_DEBUG "%s: %s ack\n", dev->name, msg); + writel(ArAck, ioaddr); + goto done; + } else if (state & Arf) { + printk(KERN_ERR "%s: %s failed\n", dev->name, msg); + writel(Arf, ioaddr); + i = -1; + goto done; + } + rmb(); + } while (++i > 0); + printk(KERN_ERR "%s: %s timeout\n", dev->name, msg); +done: + return i; +} + +static inline int dscc4_xpr_ack(struct dscc4_dev_priv *dpriv) +{ + int cur = dpriv->iqtx_current%IRQ_RING_SIZE; + s8 i = 0; + + do { + if (!(dpriv->flags & (NeedIDR | NeedIDT)) || + (dpriv->iqtx[cur] & Xpr)) + break; + smp_rmb(); + set_current_state(TASK_UNINTERRUPTIBLE); + schedule_timeout(10); + } while (++i > 0); + + return (i >= 0 ) ? i : -EAGAIN; +} + +#if 0 /* dscc4_{rx/tx}_reset are both unreliable - more tweak needed */ +static void dscc4_rx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev) +{ + unsigned long flags; + + spin_lock_irqsave(&dpriv->pci_priv->lock, flags); + /* Cf errata DS5 p.6 */ + writel(0x00000000, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4); + scc_patchl(PowerUp, 0, dpriv, dev, CCR0); + readl(dpriv->base_addr + CH0LRDA + dpriv->dev_id*4); + writel(MTFi|Rdr, dpriv->base_addr + dpriv->dev_id*0x0c + CH0CFG); + writel(Action, dpriv->base_addr + GCMDR); + spin_unlock_irqrestore(&dpriv->pci_priv->lock, flags); +} + +#endif + +#if 0 +static void dscc4_tx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev) +{ + u16 i = 0; + + /* Cf errata DS5 p.7 */ + scc_patchl(PowerUp, 0, dpriv, dev, CCR0); + scc_writel(0x00050000, dpriv, dev, CCR2); + /* + * Must be longer than the time required to fill the fifo. + */ + while (!dscc4_tx_quiescent(dpriv, dev) && ++i) { + udelay(1); + wmb(); + } + + writel(MTFi|Rdt, dpriv->base_addr + dpriv->dev_id*0x0c + CH0CFG); + if (dscc4_do_action(dev, "Rdt") < 0) + printk(KERN_ERR "%s: Tx reset failed\n", dev->name); +} +#endif + +/* TODO: (ab)use this function to refill a completely depleted RX ring. */ +static inline void dscc4_rx_skb(struct dscc4_dev_priv *dpriv, + struct net_device *dev) +{ + struct RxFD *rx_fd = dpriv->rx_fd + dpriv->rx_current%RX_RING_SIZE; + struct net_device_stats *stats = hdlc_stats(dev); + struct pci_dev *pdev = dpriv->pci_priv->pdev; + struct sk_buff *skb; + int pkt_len; + + skb = dpriv->rx_skbuff[dpriv->rx_current++%RX_RING_SIZE]; + if (!skb) { + printk(KERN_DEBUG "%s: skb=0 (%s)\n", dev->name, __FUNCTION__); + goto refill; + } + pkt_len = TO_SIZE(rx_fd->state2); + pci_unmap_single(pdev, rx_fd->data, RX_MAX(HDLC_MAX_MRU), PCI_DMA_FROMDEVICE); + if ((skb->data[--pkt_len] & FrameOk) == FrameOk) { + stats->rx_packets++; + stats->rx_bytes += pkt_len; + skb_put(skb, pkt_len); + if (netif_running(dev)) + skb->protocol = hdlc_type_trans(skb, dev); + skb->dev->last_rx = jiffies; + netif_rx(skb); + } else { + if (skb->data[pkt_len] & FrameRdo) + stats->rx_fifo_errors++; + else if (!(skb->data[pkt_len] | ~FrameCrc)) + stats->rx_crc_errors++; + else if (!(skb->data[pkt_len] | ~(FrameVfr | FrameRab))) + stats->rx_length_errors++; + else + stats->rx_errors++; + dev_kfree_skb_irq(skb); + } +refill: + while ((dpriv->rx_dirty - dpriv->rx_current) % RX_RING_SIZE) { + if (try_get_rx_skb(dpriv, dev) < 0) + break; + dpriv->rx_dirty++; + } + dscc4_rx_update(dpriv, dev); + rx_fd->state2 = 0x00000000; + rx_fd->end = 0xbabeface; +} + +static void dscc4_free1(struct pci_dev *pdev) +{ + struct dscc4_pci_priv *ppriv; + struct dscc4_dev_priv *root; + int i; + + ppriv = pci_get_drvdata(pdev); + root = ppriv->root; + + for (i = 0; i < dev_per_card; i++) + unregister_hdlc_device(dscc4_to_dev(root + i)); + + pci_set_drvdata(pdev, NULL); + + for (i = 0; i < dev_per_card; i++) + free_netdev(root[i].dev); + kfree(root); + kfree(ppriv); +} + +static int __devinit dscc4_init_one(struct pci_dev *pdev, + const struct pci_device_id *ent) +{ + struct dscc4_pci_priv *priv; + struct dscc4_dev_priv *dpriv; + void __iomem *ioaddr; + int i, rc; + + printk(KERN_DEBUG "%s", version); + + rc = pci_enable_device(pdev); + if (rc < 0) + goto out; + + rc = pci_request_region(pdev, 0, "registers"); + if (rc < 0) { + printk(KERN_ERR "%s: can't reserve MMIO region (regs)\n", + DRV_NAME); + goto err_disable_0; + } + rc = pci_request_region(pdev, 1, "LBI interface"); + if (rc < 0) { + printk(KERN_ERR "%s: can't reserve MMIO region (lbi)\n", + DRV_NAME); + goto err_free_mmio_region_1; + } + + ioaddr = ioremap(pci_resource_start(pdev, 0), + pci_resource_len(pdev, 0)); + if (!ioaddr) { + printk(KERN_ERR "%s: cannot remap MMIO region %lx @ %lx\n", + DRV_NAME, pci_resource_len(pdev, 0), + pci_resource_start(pdev, 0)); + rc = -EIO; + goto err_free_mmio_regions_2; + } + printk(KERN_DEBUG "Siemens DSCC4, MMIO at %#lx (regs), %#lx (lbi), IRQ %d\n", + pci_resource_start(pdev, 0), + pci_resource_start(pdev, 1), pdev->irq); + + /* Cf errata DS5 p.2 */ + pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xf8); + pci_set_master(pdev); + + rc = dscc4_found1(pdev, ioaddr); + if (rc < 0) + goto err_iounmap_3; + + priv = pci_get_drvdata(pdev); + + rc = request_irq(pdev->irq, dscc4_irq, SA_SHIRQ, DRV_NAME, priv->root); + if (rc < 0) { + printk(KERN_WARNING "%s: IRQ %d busy\n", DRV_NAME, pdev->irq); + goto err_release_4; + } + + /* power up/little endian/dma core controlled via lrda/ltda */ + writel(0x00000001, ioaddr + GMODE); + /* Shared interrupt queue */ + { + u32 bits; + + bits = (IRQ_RING_SIZE >> 5) - 1; + bits |= bits << 4; + bits |= bits << 8; + bits |= bits << 16; + writel(bits, ioaddr + IQLENR0); + } + /* Global interrupt queue */ + writel((u32)(((IRQ_RING_SIZE >> 5) - 1) << 20), ioaddr + IQLENR1); + priv->iqcfg = (u32 *) pci_alloc_consistent(pdev, + IRQ_RING_SIZE*sizeof(u32), &priv->iqcfg_dma); + if (!priv->iqcfg) + goto err_free_irq_5; + writel(priv->iqcfg_dma, ioaddr + IQCFG); + + rc = -ENOMEM; + + /* + * SCC 0-3 private rx/tx irq structures + * IQRX/TXi needs to be set soon. Learned it the hard way... + */ + for (i = 0; i < dev_per_card; i++) { + dpriv = priv->root + i; + dpriv->iqtx = (u32 *) pci_alloc_consistent(pdev, + IRQ_RING_SIZE*sizeof(u32), &dpriv->iqtx_dma); + if (!dpriv->iqtx) + goto err_free_iqtx_6; + writel(dpriv->iqtx_dma, ioaddr + IQTX0 + i*4); + } + for (i = 0; i < dev_per_card; i++) { + dpriv = priv->root + i; + dpriv->iqrx = (u32 *) pci_alloc_consistent(pdev, + IRQ_RING_SIZE*sizeof(u32), &dpriv->iqrx_dma); + if (!dpriv->iqrx) + goto err_free_iqrx_7; + writel(dpriv->iqrx_dma, ioaddr + IQRX0 + i*4); + } + + /* Cf application hint. Beware of hard-lock condition on threshold. */ + writel(0x42104000, ioaddr + FIFOCR1); + //writel(0x9ce69800, ioaddr + FIFOCR2); + writel(0xdef6d800, ioaddr + FIFOCR2); + //writel(0x11111111, ioaddr + FIFOCR4); + writel(0x18181818, ioaddr + FIFOCR4); + // FIXME: should depend on the chipset revision + writel(0x0000000e, ioaddr + FIFOCR3); + + writel(0xff200001, ioaddr + GCMDR); + + rc = 0; +out: + return rc; + +err_free_iqrx_7: + while (--i >= 0) { + dpriv = priv->root + i; + pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), + dpriv->iqrx, dpriv->iqrx_dma); + } + i = dev_per_card; +err_free_iqtx_6: + while (--i >= 0) { + dpriv = priv->root + i; + pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), + dpriv->iqtx, dpriv->iqtx_dma); + } + pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), priv->iqcfg, + priv->iqcfg_dma); +err_free_irq_5: + free_irq(pdev->irq, priv->root); +err_release_4: + dscc4_free1(pdev); +err_iounmap_3: + iounmap (ioaddr); +err_free_mmio_regions_2: + pci_release_region(pdev, 1); +err_free_mmio_region_1: + pci_release_region(pdev, 0); +err_disable_0: + pci_disable_device(pdev); + goto out; +}; + +/* + * Let's hope the default values are decent enough to protect my + * feet from the user's gun - Ueimor + */ +static void dscc4_init_registers(struct dscc4_dev_priv *dpriv, + struct net_device *dev) +{ + /* No interrupts, SCC core disabled. Let's relax */ + scc_writel(0x00000000, dpriv, dev, CCR0); + + scc_writel(LengthCheck | (HDLC_MAX_MRU >> 5), dpriv, dev, RLCR); + + /* + * No address recognition/crc-CCITT/cts enabled + * Shared flags transmission disabled - cf errata DS5 p.11 + * Carrier detect disabled - cf errata p.14 + * FIXME: carrier detection/polarity may be handled more gracefully. + */ + scc_writel(0x02408000, dpriv, dev, CCR1); + + /* crc not forwarded - Cf errata DS5 p.11 */ + scc_writel(0x00050008 & ~RxActivate, dpriv, dev, CCR2); + // crc forwarded + //scc_writel(0x00250008 & ~RxActivate, dpriv, dev, CCR2); +} + +static inline int dscc4_set_quartz(struct dscc4_dev_priv *dpriv, int hz) +{ + int ret = 0; + + if ((hz < 0) || (hz > DSCC4_HZ_MAX)) + ret = -EOPNOTSUPP; + else + dpriv->pci_priv->xtal_hz = hz; + + return ret; +} + +static int dscc4_found1(struct pci_dev *pdev, void __iomem *ioaddr) +{ + struct dscc4_pci_priv *ppriv; + struct dscc4_dev_priv *root; + int i, ret = -ENOMEM; + + root = kmalloc(dev_per_card*sizeof(*root), GFP_KERNEL); + if (!root) { + printk(KERN_ERR "%s: can't allocate data\n", DRV_NAME); + goto err_out; + } + memset(root, 0, dev_per_card*sizeof(*root)); + + for (i = 0; i < dev_per_card; i++) { + root[i].dev = alloc_hdlcdev(root + i); + if (!root[i].dev) + goto err_free_dev; + } + + ppriv = kmalloc(sizeof(*ppriv), GFP_KERNEL); + if (!ppriv) { + printk(KERN_ERR "%s: can't allocate private data\n", DRV_NAME); + goto err_free_dev; + } + memset(ppriv, 0, sizeof(struct dscc4_pci_priv)); + + ppriv->root = root; + spin_lock_init(&ppriv->lock); + + for (i = 0; i < dev_per_card; i++) { + struct dscc4_dev_priv *dpriv = root + i; + struct net_device *d = dscc4_to_dev(dpriv); + hdlc_device *hdlc = dev_to_hdlc(d); + + d->base_addr = (unsigned long)ioaddr; + d->init = NULL; + d->irq = pdev->irq; + d->open = dscc4_open; + d->stop = dscc4_close; + d->set_multicast_list = NULL; + d->do_ioctl = dscc4_ioctl; + d->tx_timeout = dscc4_tx_timeout; + d->watchdog_timeo = TX_TIMEOUT; + SET_MODULE_OWNER(d); + SET_NETDEV_DEV(d, &pdev->dev); + + dpriv->dev_id = i; + dpriv->pci_priv = ppriv; + dpriv->base_addr = ioaddr; + spin_lock_init(&dpriv->lock); + + hdlc->xmit = dscc4_start_xmit; + hdlc->attach = dscc4_hdlc_attach; + + dscc4_init_registers(dpriv, d); + dpriv->parity = PARITY_CRC16_PR0_CCITT; + dpriv->encoding = ENCODING_NRZ; + + ret = dscc4_init_ring(d); + if (ret < 0) + goto err_unregister; + + ret = register_hdlc_device(d); + if (ret < 0) { + printk(KERN_ERR "%s: unable to register\n", DRV_NAME); + dscc4_release_ring(dpriv); + goto err_unregister; + } + } + + ret = dscc4_set_quartz(root, quartz); + if (ret < 0) + goto err_unregister; + + pci_set_drvdata(pdev, ppriv); + return ret; + +err_unregister: + while (i-- > 0) { + dscc4_release_ring(root + i); + unregister_hdlc_device(dscc4_to_dev(root + i)); + } + kfree(ppriv); + i = dev_per_card; +err_free_dev: + while (i-- > 0) + free_netdev(root[i].dev); + kfree(root); +err_out: + return ret; +}; + +/* FIXME: get rid of the unneeded code */ +static void dscc4_timer(unsigned long data) +{ + struct net_device *dev = (struct net_device *)data; + struct dscc4_dev_priv *dpriv = dscc4_priv(dev); +// struct dscc4_pci_priv *ppriv; + + goto done; +done: + dpriv->timer.expires = jiffies + TX_TIMEOUT; + add_timer(&dpriv->timer); +} + +static void dscc4_tx_timeout(struct net_device *dev) +{ + /* FIXME: something is missing there */ +} + +static int dscc4_loopback_check(struct dscc4_dev_priv *dpriv) +{ + sync_serial_settings *settings = &dpriv->settings; + + if (settings->loopback && (settings->clock_type != CLOCK_INT)) { + struct net_device *dev = dscc4_to_dev(dpriv); + + printk(KERN_INFO "%s: loopback requires clock\n", dev->name); + return -1; + } + return 0; +} + +#ifdef CONFIG_DSCC4_PCI_RST +/* + * Some DSCC4-based cards wires the GPIO port and the PCI #RST pin together + * so as to provide a safe way to reset the asic while not the whole machine + * rebooting. + * + * This code doesn't need to be efficient. Keep It Simple + */ +static void dscc4_pci_reset(struct pci_dev *pdev, void __iomem *ioaddr) +{ + int i; + + down(&dscc4_sem); + for (i = 0; i < 16; i++) + pci_read_config_dword(pdev, i << 2, dscc4_pci_config_store + i); + + /* Maximal LBI clock divider (who cares ?) and whole GPIO range. */ + writel(0x001c0000, ioaddr + GMODE); + /* Configure GPIO port as output */ + writel(0x0000ffff, ioaddr + GPDIR); + /* Disable interruption */ + writel(0x0000ffff, ioaddr + GPIM); + + writel(0x0000ffff, ioaddr + GPDATA); + writel(0x00000000, ioaddr + GPDATA); + + /* Flush posted writes */ + readl(ioaddr + GSTAR); + + set_current_state(TASK_UNINTERRUPTIBLE); + schedule_timeout(10); + + for (i = 0; i < 16; i++) + pci_write_config_dword(pdev, i << 2, dscc4_pci_config_store[i]); + up(&dscc4_sem); +} +#else +#define dscc4_pci_reset(pdev,ioaddr) do {} while (0) +#endif /* CONFIG_DSCC4_PCI_RST */ + +static int dscc4_open(struct net_device *dev) +{ + struct dscc4_dev_priv *dpriv = dscc4_priv(dev); + struct dscc4_pci_priv *ppriv; + int ret = -EAGAIN; + + if ((dscc4_loopback_check(dpriv) < 0) || !dev->hard_start_xmit) + goto err; + + if ((ret = hdlc_open(dev))) + goto err; + + ppriv = dpriv->pci_priv; + + /* + * Due to various bugs, there is no way to reliably reset a + * specific port (manufacturer's dependant special PCI #RST wiring + * apart: it affects all ports). Thus the device goes in the best + * silent mode possible at dscc4_close() time and simply claims to + * be up if it's opened again. It still isn't possible to change + * the HDLC configuration without rebooting but at least the ports + * can be up/down ifconfig'ed without killing the host. + */ + if (dpriv->flags & FakeReset) { + dpriv->flags &= ~FakeReset; + scc_patchl(0, PowerUp, dpriv, dev, CCR0); + scc_patchl(0, 0x00050000, dpriv, dev, CCR2); + scc_writel(EventsMask, dpriv, dev, IMR); + printk(KERN_INFO "%s: up again.\n", dev->name); + goto done; + } + + /* IDT+IDR during XPR */ + dpriv->flags = NeedIDR | NeedIDT; + + scc_patchl(0, PowerUp | Vis, dpriv, dev, CCR0); + + /* + * The following is a bit paranoid... + * + * NB: the datasheet "...CEC will stay active if the SCC is in + * power-down mode or..." and CCR2.RAC = 1 are two different + * situations. + */ + if (scc_readl_star(dpriv, dev) & SccBusy) { + printk(KERN_ERR "%s busy. Try later\n", dev->name); + ret = -EAGAIN; + goto err_out; + } else + printk(KERN_INFO "%s: available. Good\n", dev->name); + + scc_writel(EventsMask, dpriv, dev, IMR); + + /* Posted write is flushed in the wait_ack loop */ + scc_writel(TxSccRes | RxSccRes, dpriv, dev, CMDR); + + if ((ret = dscc4_wait_ack_cec(dpriv, dev, "Cec")) < 0) + goto err_disable_scc_events; + + /* + * I would expect XPR near CE completion (before ? after ?). + * At worst, this code won't see a late XPR and people + * will have to re-issue an ifconfig (this is harmless). + * WARNING, a really missing XPR usually means a hardware + * reset is needed. Suggestions anyone ? + */ + if ((ret = dscc4_xpr_ack(dpriv)) < 0) { + printk(KERN_ERR "%s: %s timeout\n", DRV_NAME, "XPR"); + goto err_disable_scc_events; + } + + if (debug > 2) + dscc4_tx_print(dev, dpriv, "Open"); + +done: + netif_start_queue(dev); + + init_timer(&dpriv->timer); + dpriv->timer.expires = jiffies + 10*HZ; + dpriv->timer.data = (unsigned long)dev; + dpriv->timer.function = &dscc4_timer; + add_timer(&dpriv->timer); + netif_carrier_on(dev); + + return 0; + +err_disable_scc_events: + scc_writel(0xffffffff, dpriv, dev, IMR); + scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0); +err_out: + hdlc_close(dev); +err: + return ret; +} + +#ifdef DSCC4_POLLING +static int dscc4_tx_poll(struct dscc4_dev_priv *dpriv, struct net_device *dev) +{ + /* FIXME: it's gonna be easy (TM), for sure */ +} +#endif /* DSCC4_POLLING */ |