diff options
| author | Sony Chacko <sony.chacko@qlogic.com> | 2013-01-01 03:20:19 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2013-01-02 02:43:26 -0800 |
| commit | 7f9664525f9cb507de9198a395a111371413f230 (patch) | |
| tree | 3afa3c469348de2847dc2e82a2dfa9583c2fb617 /drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.h | |
| parent | a15ebd371992dbadb8a30367fd80cb5cd73b8fb1 (diff) | |
qlcnic: 83xx memory map and HW access routines
83xx adapter register map.
83xx hardware interface routines.
Signed-off-by: Sucheta Chakraborty <sucheta.chakraborty@qlogic.com>
Signed-off-by: Anirban Chakraborty <anirban.chakraborty@qlogic.com>
Signed-off-by: Sritej Velaga <sritej.velaga@qlogic.com>
Signed-off-by: Sony Chacko <sony.chacko@qlogic.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.h')
| -rw-r--r-- | drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.h b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.h index 937d75f939aa..9673e2bcff06 100644 --- a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.h +++ b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.h @@ -36,6 +36,14 @@ enum qlcnic_regs { #define QLC_SHARED_REG_WR32(a, addr, value) \ writel(value, ((a)->ahw->pci_base0) + ((a)->ahw->reg_tbl[addr])) +/* Read from a direct address offset from BAR0, additional registers */ +#define QLCRDX(ahw, addr) \ + readl(((ahw)->pci_base0) + ((ahw)->ext_reg_tbl[addr])) + +/* Write to a direct address offset from BAR0, additional registers */ +#define QLCWRX(ahw, addr, value) \ + writel(value, (((ahw)->pci_base0) + ((ahw)->ext_reg_tbl[addr]))) + #define QLCNIC_CMD_CONFIGURE_IP_ADDR 0x1 #define QLCNIC_CMD_CONFIG_INTRPT 0x2 #define QLCNIC_CMD_CREATE_RX_CTX 0x7 @@ -85,6 +93,7 @@ enum qlcnic_regs { #define QLCNIC_CMD_GET_LINK_STATUS 0x68 #define QLCNIC_CMD_SET_LED_CONFIG 0x69 #define QLCNIC_CMD_GET_LED_CONFIG 0x6A +#define QLCNIC_CMD_ADD_RCV_RINGS 0x0B #define QLCNIC_INTRPT_INTX 1 #define QLCNIC_INTRPT_MSIX 3 @@ -110,6 +119,13 @@ struct qlcnic_mailbox_metadata { u32 out_args; }; +/* Mailbox ownership */ +#define QLCNIC_GET_OWNER(val) ((val) & (BIT_0 | BIT_1)) + +#define QLCNIC_SET_OWNER 1 +#define QLCNIC_CLR_OWNER 0 +#define QLCNIC_MBX_TIMEOUT 10000 + #define QLCNIC_MBX_RSP_OK 1 #define QLCNIC_MBX_PORT_RSP_OK 0x1a @@ -166,4 +182,5 @@ int qlcnic_82xx_api_lock(struct qlcnic_adapter *); void qlcnic_82xx_api_unlock(struct qlcnic_adapter *); void qlcnic_82xx_napi_enable(struct qlcnic_adapter *); void qlcnic_82xx_napi_disable(struct qlcnic_adapter *); +void qlcnic_82xx_napi_del(struct qlcnic_adapter *); #endif /* __QLCNIC_HW_H_ */ |