diff options
| author | Sunil Goutham <sgoutham@marvell.com> | 2020-01-27 18:35:21 +0530 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2020-01-27 14:33:39 +0100 |
| commit | 3ca6c4c882a7f34085b170d93cf0d0e843aa00e6 (patch) | |
| tree | 01051c80c67cc06745f87f8e0bce9a3a10f6eed2 /drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h | |
| parent | abe0254333124598d1e7452c19e9e753c6bfaada (diff) | |
octeontx2-pf: Add packet transmission support
This patch adds the packet transmission support.
For a given skb prepares send queue descriptors (SQEs) and pushes them
to HW. Here driver doesn't maintain it's own SQ rings, SQEs are pushed
to HW using a silicon specific operations called LMTST. From the
instuction HW derives the transmit queue number and queues the SQE to
that queue. These LMTST instructions are designed to avoid queue
maintenance in SW and lockless behavior ie when multiple cores are trying
to add SQEs to same queue then HW will takecare of serialization, no need
for SW to hold locks.
Also supports scatter/gather.
Co-developed-by: Geetha sowjanya <gakula@marvell.com>
Signed-off-by: Geetha sowjanya <gakula@marvell.com>
Signed-off-by: Sunil Goutham <sgoutham@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h')
| -rw-r--r-- | drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h index 0944c176efa3..d9683c3bbc91 100644 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h @@ -22,6 +22,8 @@ #define OTX2_DATA_ALIGN(X) ALIGN(X, OTX2_ALIGN) #define OTX2_HEAD_ROOM OTX2_ALIGN +#define OTX2_MAX_FRAGS_IN_SQE 9 + /* Rx buffer size should be in multiples of 128bytes */ #define RCV_FRAG_LEN1(x) \ ((OTX2_HEAD_ROOM + OTX2_DATA_ALIGN(x)) + \ @@ -53,17 +55,27 @@ */ #define CQ_QCOUNT_DEFAULT 1 +struct sg_list { + u16 num_segs; + u64 skb; + u64 size[OTX2_MAX_FRAGS_IN_SQE]; + u64 dma_addr[OTX2_MAX_FRAGS_IN_SQE]; +}; + struct otx2_snd_queue { u8 aura_id; + u16 head; u16 sqe_size; u32 sqe_cnt; u16 num_sqbs; + u16 sqe_thresh; u8 sqe_per_sqb; u64 io_addr; u64 *aura_fc_addr; u64 *lmt_addr; void *sqe_base; struct qmem *sqe; + struct sg_list *sg; u16 sqb_count; u64 *sqb_ptrs; } ____cacheline_aligned_in_smp; @@ -127,4 +139,6 @@ static inline u64 otx2_iova_to_phys(void *iommu_domain, dma_addr_t dma_addr) } int otx2_napi_handler(struct napi_struct *napi, int budget); +bool otx2_sq_append_skb(struct net_device *netdev, struct otx2_snd_queue *sq, + struct sk_buff *skb, u16 qidx); #endif /* OTX2_TXRX_H */ |