diff options
| author | Praveenkumar I <ipkumar@codeaurora.org> | 2020-10-09 13:37:52 +0530 |
|---|---|---|
| committer | Miquel Raynal <miquel.raynal@bootlin.com> | 2020-12-10 22:37:31 +0100 |
| commit | bc3686021122de953858a5be4cbf6e3f1d821e79 (patch) | |
| tree | abd8778a7ca75613acff2e8cfd2ec1248ed6117b /drivers/mtd | |
| parent | efd50ff127b59d9a0f5f41ebf842d0d6ae8e4f6d (diff) | |
mtd: rawnand: qcom: Fix DMA sync on FLASH_STATUS register read
After each codeword NAND_FLASH_STATUS is read for possible operational
failures. But there is no DMA sync for CPU operation before reading it
and this leads to incorrect or older copy of DMA buffer in reg_read_buf.
This patch adds the DMA sync on reg_read_buf for CPU before reading it.
Fixes: 5bc36b2bf6e2 ("mtd: rawnand: qcom: check for operation errors in case of raw read")
Cc: stable@vger.kernel.org
Signed-off-by: Praveenkumar I <ipkumar@codeaurora.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/1602230872-25616-1-git-send-email-ipkumar@codeaurora.org
Diffstat (limited to 'drivers/mtd')
| -rw-r--r-- | drivers/mtd/nand/raw/qcom_nandc.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index 777fb0de0680..dfc17a28a06b 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -1570,6 +1570,8 @@ static int check_flash_errors(struct qcom_nand_host *host, int cw_cnt) struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); int i; + nandc_read_buffer_sync(nandc, true); + for (i = 0; i < cw_cnt; i++) { u32 flash = le32_to_cpu(nandc->reg_read_buf[i]); |