diff options
| author | Tudor Ambarus <tudor.ambarus@microchip.com> | 2019-11-07 08:42:01 +0000 |
|---|---|---|
| committer | Tudor Ambarus <tudor.ambarus@microchip.com> | 2019-11-11 08:56:37 +0200 |
| commit | bb2dc7f46ad897ba1c2d8ae773c77601ba240932 (patch) | |
| tree | ed1ae10cccda1b961f4b40edfb684af5e82a77ff /drivers/mtd/spi-nor | |
| parent | 4da11da15a7cc56432a92ee47748c95cf29dbe3d (diff) | |
mtd: spi-nor: Rename CR_QUAD_EN_SPAN to SR2_QUAD_EN_BIT1
JEDEC Basic Flash Parameter Table, 15th DWORD, bits 22:20,
refers to this bit as "bit 1 of the status register 2".
Rename the macro accordingly.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Diffstat (limited to 'drivers/mtd/spi-nor')
| -rw-r--r-- | drivers/mtd/spi-nor/spi-nor.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index d33ad56d3b67..8c59b5220e2a 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1026,7 +1026,7 @@ static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1) * Write Status (01h) command is available just for the cases * in which the QE bit is described in SR2 at BIT(1). */ - sr_cr[1] = CR_QUAD_EN_SPAN; + sr_cr[1] = SR2_QUAD_EN_BIT1; } else { sr_cr[1] = 0; } @@ -2074,7 +2074,7 @@ static int spansion_no_read_cr_quad_enable(struct spi_nor *nor) if (ret) return ret; - sr_cr[1] = CR_QUAD_EN_SPAN; + sr_cr[1] = SR2_QUAD_EN_BIT1; ret = spi_nor_write_sr(nor, sr_cr, 2); if (ret) @@ -2118,10 +2118,10 @@ static int spansion_read_cr_quad_enable(struct spi_nor *nor) if (ret) return ret; - if (sr_cr[1] & CR_QUAD_EN_SPAN) + if (sr_cr[1] & SR2_QUAD_EN_BIT1) return 0; - sr_cr[1] |= CR_QUAD_EN_SPAN; + sr_cr[1] |= SR2_QUAD_EN_BIT1; /* Keep the current value of the Status Register. */ ret = spi_nor_read_sr(nor, sr_cr); |