diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2020-04-02 16:45:46 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2020-04-02 16:45:46 -0700 |
commit | e109f506074152b7241bcbd3949a099e776cb802 (patch) | |
tree | 19a5c7e07a4f791cf02c060a3a4d370315fe1cfa /drivers/mtd/spi-nor/sfdp.h | |
parent | e964f1e04a1ce562f0d748b29326244d3cb35ba4 (diff) | |
parent | 025a06c1104cd8995646b761d117816b5f28c873 (diff) |
Merge tag 'mtd/for-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
Pull MTD updates from Miquel Raynal:
"MTD core changes:
- Fix issue where write_cached_data() fails but write() still returns
success
- maps: sa1100-flash: Replace zero-length array with flexible-array
member
- phram: Fix a double free issue in error path
- Convert fallthrough comments into statements
- MAINTAINERS: Add the IRC channel to the MTD related subsystems
Raw NAND core changes:
- Add support for manufacturer specific suspend/resume operation
- Add support for manufacturer specific lock/unlock operation
- Replace zero-length array with flexible-array member
- Fix a typo ("manufecturer")
- Ensure nand_soft_waitrdy wait period is enough
Raw NAND controller driver changes:
- Brcmnand:
* Add support for flash-edu for dma transfers (+ bindings)
- Cadence:
* Reinit completion before executing a new command
* Change bad block marker size
* Fix the calculation of the avaialble OOB size
* Get meta data size from registers
- Qualcom:
* Use dma_request_chan() instead dma_request_slave_channel()
* Release resources on failure within qcom_nandc_alloc()
- Allwinner:
* Use dma_request_chan() instead dma_request_slave_channel()
- Marvell:
* Use dma_request_chan() instead dma_request_slave_channel()
* Release DMA channel on error
- Freescale:
* Use dma_request_chan() instead dma_request_slave_channel()
- Macronix:
* Add support for Macronix NAND randomizer (+ bindings)
- Ams-delta:
* Rename structures and functions to gpio_nand*
* Make the driver custom I/O ready
* Drop useless local variable
* Support custom driver initialisation
* Add module device tables
* Handle more GPIO pins as optional
* Make read pulses optional
* Don't hardcode read/write pulse widths
* Push inversion handling to gpiolib
* Enable OF partition info support
* Drop board specific partition info
* Use struct gpio_nand_platdata
* Write protect device during probe
- Ingenic:
* Use devm_platform_ioremap_resource()
* Add dependency on MIPS || COMPILE_TEST
- Denali:
* Deassert write protect pin
- ST:
* Use dma_request_chan() instead dma_request_slave_channel()
Raw NAND chip driver changes:
- Toshiba:
* Support reading the number of bitflips for BENAND (Built-in ECC NAND)
- Macronix:
* Add support for deep power down mode
* Add support for block protection
SPI-NAND core changes:
- Do not erase the block before writing a bad block marker
- Explicitly use MTD_OPS_RAW to write the bad block marker to OOB
- Stop using spinand->oobbuf for buffering bad block markers
- Rework detect procedure for different READ_ID operation
SPI-NAND driver changes:
- Toshiba:
* Support for new Kioxia Serial NAND
* Rename function name to change suffix and prefix (8Gbit)
* Add comment about Kioxia ID
- Micron:
* Add new Micron SPI NAND devices with multiple dies
* Add M70A series Micron SPI NAND devices
* identify SPI NAND device with Continuous Read mode
* Add new Micron SPI NAND devices
* Describe the SPI NAND device MT29F2G01ABAGD
* Generalize the OOB layout structure and function names
SPI NOR core changes:
- Move all the manufacturer specific quirks/code out of the core, to
make the core logic more readable and thus ease maintenance.
- Move the SFDP logic out of the core, it provides a better
separation between the SFDP parsing and core logic.
- Trim what is exposed in spi-nor.h. The SPI NOR controllers drivers
must not be able to use structures that are meant just for the SPI
NOR core.
- Use the spi-mem direct mapping API to let advanced controllers
optimize the read/write operations when they support direct
mapping.
- Add generic formula for the Status Register block protection
handling. It fixes some long standing locking limitations and eases
the addition of the 4bit block protection support.
- Add block protection support for flashes with 4 block protection
bits in the Status Register.
SPI NOR controller drivers changes:
- The mtk-quadspi driver is replaced by the new spi-mem spi-mtk-nor
driver.
- Merge tag 'mtk-mtd-spi-move' into spi-nor/next to avoid conflicts.
HyperBus changes:
- Print error msg when compatible is wrong or missing
- Move mapping of direct access window from core to individual
drivers"
* tag 'mtd/for-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (103 commits)
mtd: Convert fallthrough comments into statements
mtd: rawnand: toshiba: Support reading the number of bitflips for BENAND (Built-in ECC NAND)
MAINTAINERS: Add the IRC channel to the MTD related subsystems
mtd: Fix issue where write_cached_data() fails but write() still returns success
mtd: maps: sa1100-flash: Replace zero-length array with flexible-array member
mtd: phram: fix a double free issue in error path
mtd: spinand: toshiba: Support for new Kioxia Serial NAND
mtd: spinand: toshiba: Rename function name to change suffix and prefix (8Gbit)
mtd: rawnand: macronix: Add support for deep power down mode
mtd: rawnand: Add support for manufacturer specific suspend/resume operation
mtd: spi-nor: Enable locking for n25q512ax3/n25q512a
mtd: spi-nor: Add SR 4bit block protection support
mtd: spi-nor: Add generic formula for SR block protection handling
mtd: spi-nor: Set all BP bits to one when lock_len == mtd->size
mtd: spi-nor: controllers: aspeed-smc: Replace zero-length array with flexible-array member
mtd: spi-nor: Clear WEL bit when erase or program errors occur
MAINTAINERS: update entry after SPI NOR controller move
mtd: spi-nor: Trim what is exposed in spi-nor.h
mtd: spi-nor: Drop the MFR definitions
mtd: spi-nor: Get rid of the now empty spi_nor_ids[] table
...
Diffstat (limited to 'drivers/mtd/spi-nor/sfdp.h')
-rw-r--r-- | drivers/mtd/spi-nor/sfdp.h | 98 |
1 files changed, 98 insertions, 0 deletions
diff --git a/drivers/mtd/spi-nor/sfdp.h b/drivers/mtd/spi-nor/sfdp.h new file mode 100644 index 000000000000..e0a8ded04890 --- /dev/null +++ b/drivers/mtd/spi-nor/sfdp.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2005, Intec Automation Inc. + * Copyright (C) 2014, Freescale Semiconductor, Inc. + */ + +#ifndef __LINUX_MTD_SFDP_H +#define __LINUX_MTD_SFDP_H + +/* Basic Flash Parameter Table */ + +/* + * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs. + * They are indexed from 1 but C arrays are indexed from 0. + */ +#define BFPT_DWORD(i) ((i) - 1) +#define BFPT_DWORD_MAX 16 + +struct sfdp_bfpt { + u32 dwords[BFPT_DWORD_MAX]; +}; + +/* The first version of JESD216 defined only 9 DWORDs. */ +#define BFPT_DWORD_MAX_JESD216 9 + +/* 1st DWORD. */ +#define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16) +#define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17) +#define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17) +#define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17) +#define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17) +#define BFPT_DWORD1_DTR BIT(19) +#define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20) +#define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21) +#define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22) + +/* 5th DWORD. */ +#define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0) +#define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4) + +/* 11th DWORD. */ +#define BFPT_DWORD11_PAGE_SIZE_SHIFT 4 +#define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4) + +/* 15th DWORD. */ + +/* + * (from JESD216 rev B) + * Quad Enable Requirements (QER): + * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4 + * reads based on instruction. DQ3/HOLD# functions are hold during + * instruction phase. + * - 001b: QE is bit 1 of status register 2. It is set via Write Status with + * two data bytes where bit 1 of the second byte is one. + * [...] + * Writing only one byte to the status register has the side-effect of + * clearing status register 2, including the QE bit. The 100b code is + * used if writing one byte to the status register does not modify + * status register 2. + * - 010b: QE is bit 6 of status register 1. It is set via Write Status with + * one data byte where bit 6 is one. + * [...] + * - 011b: QE is bit 7 of status register 2. It is set via Write status + * register 2 instruction 3Eh with one data byte where bit 7 is one. + * [...] + * The status register 2 is read using instruction 3Fh. + * - 100b: QE is bit 1 of status register 2. It is set via Write Status with + * two data bytes where bit 1 of the second byte is one. + * [...] + * In contrast to the 001b code, writing one byte to the status + * register does not modify status register 2. + * - 101b: QE is bit 1 of status register 2. Status register 1 is read using + * Read Status instruction 05h. Status register2 is read using + * instruction 35h. QE is set via Write Status instruction 01h with + * two data bytes where bit 1 of the second byte is one. + * [...] + */ +#define BFPT_DWORD15_QER_MASK GENMASK(22, 20) +#define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */ +#define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20) +#define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */ +#define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20) +#define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20) +#define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */ + +struct sfdp_parameter_header { + u8 id_lsb; + u8 minor; + u8 major; + u8 length; /* in double words */ + u8 parameter_table_pointer[3]; /* byte address */ + u8 id_msb; +}; + +int spi_nor_parse_sfdp(struct spi_nor *nor, + struct spi_nor_flash_parameter *params); + +#endif /* __LINUX_MTD_SFDP_H */ |