[media] drx-j: get rid of dead code

There are large chunks of code at drx-j that aren't used. Most
of them are due to analog TV support. Well, just enabling them
won't make analog support work, as devices with DRX and analog
support requires an extra chip (avf4910).

We don't have drivers for it, nor the current device that uses
this frontend has support for analog TV.

So, let's just get rid of this code. If latter needed, this
patch can easily be reverted from git history.

Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>

1 files changed, 0 insertions, 8513 deletions

diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c
index a8fd53b612ae..e8c890800904 100644
--- a/drivers/media/dvb-frontends/drx39xyj/drxj.c
+++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c
@@ -1028,13 +1028,6 @@ ctrl_power_mode(struct drx_demod_instance *demod, enum drx_power_mode *mode);
 
 static int power_down_aud(struct drx_demod_instance *demod);
 
-#if 0
-static int power_up_aud(struct drx_demod_instance *demod, bool set_standard);
-
-static int
-aud_ctrl_set_standard(struct drx_demod_instance *demod, enum drx_aud_standard *standard);
-#endif
-
 static int
 ctrl_set_cfg_pre_saw(struct drx_demod_instance *demod, struct drxj_cfg_pre_saw *pre_saw);
 
@@ -1047,97 +1040,6 @@ ctrl_set_cfg_afe_gain(struct drx_demod_instance *demod, struct drxj_cfg_afe_gain
 /*============================================================================*/
 /*============================================================================*/
 
-#if 0
-/**
-* \fn void mult32(u32 a, u32 b, u32 *h, u32 *l)
-* \brief 32bitsx32bits signed multiplication
-* \param a 32 bits multiplicant, typecast from signed to unisgned
-* \param b 32 bits multiplier, typecast from signed to unisgned
-* \param h pointer to high part 64 bits result, typecast from signed to unisgned
-* \param l pointer to low part 64 bits result
-*
-* For the 2n+n addition a + b:
-* if a >= 0, then h += 0 (sign extension = 0)
-* but if a < 0, then h += 2^n-1 ==> h -= 1.
-*
-* Also, if a + b < 2^n, then a + b  >= a && a + b >= b
-* but if a + b >= 2^n, then R = a + b - 2^n,
-* and because a < 2^n && b < 2*n ==> R < a && R < b.
-* Therefore, to detect overflow, simply compare the addition result with
-* one of the operands; if the result is smaller, overflow has occurred and
-* h must be incremented.
-*
-* Booth multiplication uses additions and subtractions to reduce the number
-* of iterations. This is done by taking three subsequent bits abc and calculating
-* the following multiplication factor: -2a + b + c. This factor is multiplied
-* by the second operand and added to the result. Next, the first operand is
-* shifted two bits (hence one of the three bits is reused) and the process
-* repeated. The last iteration has only two bits left, but we simply add
-* a zero to the end.
-*
-* Hence: (n=4)
-*  1 * a =  0 * 4a + 1 * a
-*  2 * a =  1 * 4a - 2 * a
-*  3 * a =  1 * 4a - 1 * a
-* -1 * a =  0 * 4a - 1 * a
-* -5 * a = -1 * 4a - 1 * a
-*
-* etc.
-*
-* Note that the function is type size independent. Any unsigned integer type
-* can be substituted for booth_t.
-*
-*/
-
-#define DRX_IS_BOOTH_NEGATIVE(__a)  (((__a) & (1 << (sizeof(u32) * 8 - 1))) != 0)
-
-static void mult32(u32 a, u32 b, u32 *h, u32 *l)
-{
-	unsigned int i;
-	*h = *l = 0;
-
-	/* n/2 iterations; shift operand a left two bits after each iteration.      */
-	/* This automatically appends a zero to the operand for the last iteration. */
-	for (i = 0; i < sizeof(a) * 8; i += 2, a = a << 2) {
-		/* Shift result left two bits */
-		*h = (*h << 2) + (*l >> (sizeof(*l) * 8 - 2));
-		*l = (*l << 2);
-
-		/* Take the first three bits of operand a for the Booth conversion: */
-		/* 0, 7: do nothing  */
-		/* 1, 2: add b       */
-		/* 3   : add 2b      */
-		/* 4   : subtract 2b */
-		/* 5, 6: subtract b  */
-		switch (a >> (sizeof(a) * 8 - 3)) {
-		case 3:
-			*l += b;
-			*h = *h - DRX_IS_BOOTH_NEGATIVE(b) + (*l < b);
-		case 1:
-		case 2:
-			*l += b;
-			*h = *h - DRX_IS_BOOTH_NEGATIVE(b) + (*l < b);
-			break;
-		case 4:
-			*l -= b;
-			*h = *h - !DRX_IS_BOOTH_NEGATIVE(b) + !b + (*l <
-								    ((u32)
-								     (-
-								      ((s32)
-								       b))));
-		case 5:
-		case 6:
-			*l -= b;
-			*h = *h - !DRX_IS_BOOTH_NEGATIVE(b) + !b + (*l <
-								    ((u32)
-								     (-
-								      ((s32)
-								       b))));
-			break;
-		}
-	}
-}
-#endif
 
 /*============================================================================*/
 
@@ -1331,108 +1233,6 @@ static u32 frac_times1e6(u32 N, u32 D)
 
 /*============================================================================*/
 
-#if 0
-/**
-* \brief Compute: 100 * 10^( gd_b / 200 ).
-* \param  u32   gd_b      Gain in 0.1dB
-* \return u32            Gainfactor in 0.01 resolution
-*
-*/
-static u32 d_b2lin_times100(u32 gd_b)
-{
-	u32 result = 0;
-	u32 nr6d_b_steps = 0;
-	u32 remainder = 0;
-	u32 remainder_fac = 0;
-
-	/* start with factors 2 (6.02dB) */
-	nr6d_b_steps = gd_b * 1000UL / 60206UL;
-	if (nr6d_b_steps > 17) {
-		/* Result max overflow if > log2( maxu32 / 2e4 ) ~= 17.7 */
-		return MAX_U32;
-	}
-	result = (1 << nr6d_b_steps);
-
-	/* calculate remaining factor,
-	   poly approximation of 10^(gd_b/200):
-
-	   y = 1E-04x2 + 0.0106x + 1.0026
-
-	   max deviation < 0.005 for range x = [0 ... 60]
-	 */
-	remainder = ((gd_b * 1000UL) % 60206UL) / 1000UL;
-	/* using 1e-4 for poly calculation  */
-	remainder_fac = 1 * remainder * remainder;
-	remainder_fac += 106 * remainder;
-	remainder_fac += 10026;
-
-	/* multiply by remaining factor */
-	result *= remainder_fac;
-
-	/* conversion from 1e-4 to 1e-2 */
-	return (result + 50) / 100;
-}
-
-#define FRAC_FLOOR    0
-#define FRAC_CEIL     1
-#define FRAC_ROUND    2
-/**
-* \fn u32 frac( u32 N, u32 D, u16 RC )
-* \brief Compute: N/D.
-* \param N nominator 32-bits.
-* \param D denominator 32-bits.
-* \param RC-result correction: 0-floor; 1-ceil; 2-round
-* \return u32
-* \retval N/D, 32 bits
-*
-* If D=0 returns 0
-*/
-static u32 frac(u32 N, u32 D, u16 RC)
-{
-	u32 remainder = 0;
-	u32 frac = 0;
-	u16 bit_cnt = 32;
-
-	if (D == 0) {
-		frac = 0;
-		remainder = 0;
-
-		return frac;
-	}
-
-	if (D > N) {
-		frac = 0;
-		remainder = N;
-	} else {
-		remainder = 0;
-		frac = N;
-		while (bit_cnt-- > 0) {
-			remainder <<= 1;
-			remainder |= ((frac & 0x80000000) >> 31);
-			frac <<= 1;
-			if (remainder < D) {
-				frac &= 0xFFFFFFFE;
-			} else {
-				remainder -= D;
-				frac |= 0x1;
-			}
-		}
-
-		/* result correction if needed */
-		if ((RC == FRAC_CEIL) && (remainder != 0)) {
-			/* ceil the result */
-			/*(remainder is not zero -> value behind decimal point exists) */
-			frac++;
-		}
-		if ((RC == FRAC_ROUND) && (remainder >= D >> 1)) {
-			/* remainder is bigger from D/2 -> round the result */
-			frac++;
-		}
-	}
-
-	return frac;
-}
-#endif
 
 /**
 * \brief Values for NICAM prescaler gain. Computed from dB to integer
@@ -3542,67 +3342,6 @@ rw_error:
 
 /*----------------------------------------------------------------------------*/
 
-#if 0
-/**
-* \fn int ctrl_get_cfg_mpeg_output()
-* \brief Get MPEG output configuration of the device.
-* \param devmod  Pointer to demodulator instance.
-* \param cfg_data Pointer to MPEG output configuaration struct.
-* \return int.
-*
-*  Retrieve MPEG output configuartion.
-*
-*/
-static int
-ctrl_get_cfg_mpeg_output(struct drx_demod_instance *demod, struct drx_cfg_mpeg_output *cfg_data)
-{
-	struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
-	struct drx_common_attr *common_attr = (struct drx_common_attr *) (NULL);
-	enum drx_lock_status lock_status = DRX_NOT_LOCKED;
-	int rc;
-	u32 rate_reg = 0;
-	u32 data64hi = 0;
-	u32 data64lo = 0;
-
-	if (cfg_data == NULL)
-		return -EINVAL;
-
-	dev_addr = demod->my_i2c_dev_addr;
-	common_attr = demod->my_common_attr;
-
-	cfg_data->enable_mpeg_output = common_attr->mpeg_cfg.enable_mpeg_output;
-	cfg_data->insert_rs_byte = common_attr->mpeg_cfg.insert_rs_byte;
-	cfg_data->enable_parallel = common_attr->mpeg_cfg.enable_parallel;
-	cfg_data->invert_data = common_attr->mpeg_cfg.invert_data;
-	cfg_data->invert_err = common_attr->mpeg_cfg.invert_err;
-	cfg_data->invert_str = common_attr->mpeg_cfg.invert_str;
-	cfg_data->invert_val = common_attr->mpeg_cfg.invert_val;
-	cfg_data->invert_clk = common_attr->mpeg_cfg.invert_clk;
-	cfg_data->static_clk = common_attr->mpeg_cfg.static_clk;
-	cfg_data->bitrate = 0;
-
-	rc = ctrl_lock_status(demod, &lock_status);
-	if (rc != 0) {
-		pr_err("error %d\n", rc);
-		goto rw_error;
-	}
-	if ((lock_status == DRX_LOCKED)) {
-		rc = drxdap_fasi_read_reg32(dev_addr, FEC_OC_RCN_DYN_RATE_LO__A, &rate_reg, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-		/* Frcn_rate = rate_reg * Fsys / 2 ^ 25 */
-		mult32(rate_reg, common_attr->sys_clock_freq * 1000, &data64hi,
-		       &data64lo);
-		cfg_data->bitrate = (data64hi << 7) | (data64lo >> 25);
-	}
-
-	return 0;
-rw_error:
-	return -EIO;
-}
-#endif
 
 /*----------------------------------------------------------------------------*/
 /* MPEG Output Configuration Functions - end                                  */
@@ -3729,40 +3468,6 @@ rw_error:
 
 /*----------------------------------------------------------------------------*/
 /**
-* \fn int set_mpeg_output_clock_rate()
-* \brief Set MPEG output clock rate.
-* \param devmod  Pointer to demodulator instance.
-* \return int.
-*
-* This routine should be called during a set channel of QAM/VSB
-*
-*/
-#if 0
-static int set_mpeg_output_clock_rate(struct drx_demod_instance *demod)
-{
-	struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
-	struct i2c_device_addr *dev_addr = (struct i2c_device_addr *)(NULL);
-	int rc;
-
-	dev_addr = demod->my_i2c_dev_addr;
-	ext_attr = (struct drxj_data *) demod->my_ext_attr;
-
-	if (ext_attr->mpeg_output_clock_rate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO) {
-		rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_PERIOD__A, ext_attr->mpeg_output_clock_rate - 1, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-	}
-
-	return 0;
-rw_error:
-	return -EIO;
-}
-#endif
-
-/*----------------------------------------------------------------------------*/
-/**
 * \fn int set_mpeg_start_width()
 * \brief Set MPEG start width.
 * \param devmod  Pointer to demodulator instance.
@@ -3805,165 +3510,6 @@ rw_error:
 	return -EIO;
 }
 
-#if 0
-/*----------------------------------------------------------------------------*/
-/**
-* \fn int ctrl_set_cfg_mpeg_output_misc()
-* \brief Set miscellaneous configuartions
-* \param devmod  Pointer to demodulator instance.
-* \param cfg_data pDRXJCfgMisc_t
-* \return int.
-*
-*  This routine can be used to set configuartion options that are DRXJ
-*  specific and/or added to the requirements at a late stage.
-*
-*/
-static int
-ctrl_set_cfg_mpeg_output_misc(struct drx_demod_instance *demod,
-			      struct drxj_cfg_mpeg_output_misc *cfg_data)
-{
-	struct drxj_data *ext_attr = NULL;
-	int rc;
-
-	if (cfg_data == NULL)
-		return -EINVAL;
-
-	ext_attr = demod->my_ext_attr;
-
-	/*
-	   Set disable TEI bit handling flag.
-	   TEI must be left untouched by device in case of BER measurements using
-	   external equipment that is unable to ignore the TEI bit in the TS.
-	   Default will false (enable TEI bit handling).
-	   Reverse output bit order. Default is false (msb on MD7 (parallel) or out first (serial)).
-	   Set clock rate. Default is auto that is derived from symbol rate.
-	   The flags and values will also be used to set registers during a set channel.
-	 */
-	ext_attr->disable_te_ihandling = cfg_data->disable_tei_handling;
-	ext_attr->bit_reverse_mpeg_outout = cfg_data->bit_reverse_mpeg_outout;
-	ext_attr->mpeg_output_clock_rate = cfg_data->mpeg_output_clock_rate;
-	ext_attr->mpeg_start_width = cfg_data->mpeg_start_width;
-	/* Don't care what the active standard is, activate setting immediatly */
-	rc = set_mpegtei_handling(demod);
-	if (rc != 0) {
-		pr_err("error %d\n", rc);
-		goto rw_error;
-	}
-	rc = bit_reverse_mpeg_output(demod);
-	if (rc != 0) {
-		pr_err("error %d\n", rc);
-		goto rw_error;
-	}
-	rc = set_mpeg_output_clock_rate(demod);
-	if (rc != 0) {
-		pr_err("error %d\n", rc);
-		goto rw_error;
-	}
-	rc = set_mpeg_start_width(demod);
-	if (rc != 0) {
-		pr_err("error %d\n", rc);
-		goto rw_error;
-	}
-
-	return 0;
-rw_error:
-	return -EIO;
-}
-
-/*----------------------------------------------------------------------------*/
-
-/**
-* \fn int ctrl_get_cfg_mpeg_output_misc()
-* \brief Get miscellaneous configuartions.
-* \param devmod  Pointer to demodulator instance.
-* \param cfg_data Pointer to DRXJCfgMisc_t.
-* \return int.
-*
-*  This routine can be used to retreive the current setting of the configuartion
-*  options that are DRXJ specific and/or added to the requirements at a
-*  late stage.
-*
-*/
-static int
-ctrl_get_cfg_mpeg_output_misc(struct drx_demod_instance *demod,
-			      struct drxj_cfg_mpeg_output_misc *cfg_data)
-{
-	struct drxj_data *ext_attr = NULL;
-	int rc;
-	u16 data = 0;
-
-	if (cfg_data == NULL)
-		return -EINVAL;
-
-	ext_attr = (struct drxj_data *) demod->my_ext_attr;
-	cfg_data->disable_tei_handling = ext_attr->disable_te_ihandling;
-	cfg_data->bit_reverse_mpeg_outout = ext_attr->bit_reverse_mpeg_outout;
-	cfg_data->mpeg_start_width = ext_attr->mpeg_start_width;
-	if (ext_attr->mpeg_output_clock_rate != DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO) {
-		cfg_data->mpeg_output_clock_rate = ext_attr->mpeg_output_clock_rate;
-	} else {
-		rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, FEC_OC_DTO_PERIOD__A, &data, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-		cfg_data->mpeg_output_clock_rate =
-		    (enum drxj_mpeg_output_clock_rate) (data + 1);
-	}
-
-	return 0;
-rw_error:
-	return -EIO;
-}
-
-/*----------------------------------------------------------------------------*/
-
-/**
-* \fn int ctrl_get_cfg_hw_cfg()
-* \brief Get HW configuartions.
-* \param devmod  Pointer to demodulator instance.
-* \param cfg_data Pointer to Bool.
-* \return int.
-*
-*  This routine can be used to retreive the current setting of the configuartion
-*  options that are DRXJ specific and/or added to the requirements at a
-*  late stage.
-*
-*/
-static int
-ctrl_get_cfg_hw_cfg(struct drx_demod_instance *demod, struct drxj_cfg_hw_cfg *cfg_data)
-{
-	int rc;
-	u16 data = 0;
-
-	if (cfg_data == NULL)
-		return -EINVAL;
-
-	rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0);
-	if (rc != 0) {
-		pr_err("error %d\n", rc);
-		goto rw_error;
-	}
-	rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_OHW_CFG__A, &data, 0);
-	if (rc != 0) {
-		pr_err("error %d\n", rc);
-		goto rw_error;
-	}
-	rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
-	if (rc != 0) {
-		pr_err("error %d\n", rc);
-		goto rw_error;
-	}
-
-	cfg_data->i2c_speed = (enum drxji2c_speed) ((data >> 6) & 0x1);
-	cfg_data->xtal_freq = (enum drxj_xtal_freq) (data & 0x3);
-
-	return 0;
-rw_error:
-	return -EIO;
-}
-#endif
-
 /*----------------------------------------------------------------------------*/
 /* miscellaneous configuartions - end                             */
 /*----------------------------------------------------------------------------*/
@@ -4108,49 +3654,6 @@ rw_error:
 	return -EIO;
 }
 
-#if 0
-/*============================================================================*/
-/**
-* \fn int ctrl_getuio_cfg()
-* \brief Get modus oprandi UIO.
-* \param demod Pointer to demodulator instance.
-* \param uio_cfg Pointer to a configuration setting for a certain UIO.
-* \return int.
-*/
-static int ctrl_getuio_cfg(struct drx_demod_instance *demod, struct drxuio_cfg *uio_cfg)
-{
-
-	struct drxj_data *ext_attr = (struct drxj_data *) NULL;
-	enum drxuio_mode *uio_mode[4] = { NULL };
-	bool *uio_available[4] = { NULL };
-
-	ext_attr = demod->my_ext_attr;
-
-	uio_mode[DRX_UIO1] = &ext_attr->uio_sma_tx_mode;
-	uio_mode[DRX_UIO2] = &ext_attr->uio_sma_rx_mode;
-	uio_mode[DRX_UIO3] = &ext_attr->uio_gpio_mode;
-	uio_mode[DRX_UIO4] = &ext_attr->uio_irqn_mode;
-
-	uio_available[DRX_UIO1] = &ext_attr->has_smatx;
-	uio_available[DRX_UIO2] = &ext_attr->has_smarx;
-	uio_available[DRX_UIO3] = &ext_attr->has_gpio;
-	uio_available[DRX_UIO4] = &ext_attr->has_irqn;
-
-	if (uio_cfg == NULL)
-		return -EINVAL;
-
-	if ((uio_cfg->uio > DRX_UIO4) || (uio_cfg->uio < DRX_UIO1))
-		return -EINVAL;
-
-	if (!*uio_available[uio_cfg->uio])
-		return -EIO;
-
-	uio_cfg->mode = *uio_mode[uio_cfg->uio];
-
-	return 0;
-}
-#endif
-
 /**
 * \fn int ctrl_uio_write()
 * \brief Write to a UIO.
@@ -4353,186 +3856,6 @@ rw_error:
 	return -EIO;
 }
 
-#if 0
-/**
-*\fn int ctrl_uio_read
-*\brief Read from a UIO.
-* \param demod Pointer to demodulator instance.
-* \param uio_data Pointer to data container for a certain UIO.
-* \return int.
-*/
-static int ctrl_uio_read(struct drx_demod_instance *demod, struct drxuio_data *uio_data)
-{
-	struct drxj_data *ext_attr = (struct drxj_data *) (NULL);
-	int rc;
-	u16 pin_cfg_value = 0;
-	u16 value = 0;
-
-	if ((uio_data == NULL) || (demod == NULL))
-		return -EINVAL;
-
-	ext_attr = (struct drxj_data *) demod->my_ext_attr;
-
-	/*  Write magic word to enable pdr reg write               */
-	rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
-	if (rc != 0) {
-		pr_err("error %d\n", rc);
-		goto rw_error;
-	}
-	switch (uio_data->uio) {
-      /*====================================================================*/
-	case DRX_UIO1:
-		/* DRX_UIO1: SMA_TX UIO-1 */
-		if (!ext_attr->has_smatx)
-			return -EIO;
-
-		if (ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_READWRITE)
-			return -EIO;
-
-		pin_cfg_value = 0;
-		/* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
-		pin_cfg_value |= 0x0110;
-		/* io_pad_cfg_mode output mode is drive always */
-		/* io_pad_cfg_drive is set to power 2 (23 mA) */
-
-		/* write to io pad configuration register - input mode */
-		rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-
-		rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_IN_LO__A, &value, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-		if ((value & 0x8000) != 0) {	/* check 15th bit - 1st UIO */
-			uio_data->value = true;
-		} else {
-			uio_data->value = false;
-		}
-		break;
-   /*======================================================================*/
-	case DRX_UIO2:
-		/* DRX_UIO2: SMA_RX UIO-2 */
-		if (!ext_attr->has_smarx)
-			return -EIO;
-
-		if (ext_attr->uio_sma_rx_mode != DRX_UIO_MODE_READWRITE)
-			return -EIO;
-
-		pin_cfg_value = 0;
-		/* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
-		pin_cfg_value |= 0x0110;
-		/* io_pad_cfg_mode output mode is drive always */
-		/* io_pad_cfg_drive is set to power 2 (23 mA) */
-
-		/* write to io pad configuration register - input mode */
-		rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-
-		rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_IN_LO__A, &value, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-
-		if ((value & 0x4000) != 0)	/* check 14th bit - 2nd UIO */
-			uio_data->value = true;
-		else
-			uio_data->value = false;
-
-		break;
-   /*=====================================================================*/
-	case DRX_UIO3:
-		/* DRX_UIO3: GPIO UIO-3 */
-		if (!ext_attr->has_gpio)
-			return -EIO;
-
-		if (ext_attr->uio_gpio_mode != DRX_UIO_MODE_READWRITE)
-			return -EIO;
-
-		pin_cfg_value = 0;
-		/* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
-		pin_cfg_value |= 0x0110;
-		/* io_pad_cfg_mode output mode is drive always */
-		/* io_pad_cfg_drive is set to power 2 (23 mA) */
-
-		/* write to io pad configuration register - input mode */
-		rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, pin_cfg_value, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-
-		/* read io input data registar */
-		rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_IN_HI__A, &value, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-		if ((value & 0x0004) != 0) {	/* check 2nd bit - 3rd UIO */
-			uio_data->value = true;
-		} else {
-			uio_data->value = false;
-		}
-		break;
-   /*=====================================================================*/
-	case DRX_UIO4:
-		/* DRX_UIO4: IRQN UIO-4 */
-		if (!ext_attr->has_irqn)
-			return -EIO;
-
-		if (ext_attr->uio_irqn_mode != DRX_UIO_MODE_READWRITE)
-			return -EIO;
-
-		pin_cfg_value = 0;
-		/* io_pad_cfg register (8 bit reg.) MSB bit is 1 (default value) */
-		pin_cfg_value |= 0x0110;
-		/* io_pad_cfg_mode output mode is drive always */
-		/* io_pad_cfg_drive is set to power 2 (23 mA) */
-
-		/* write to io pad configuration register - input mode */
-		rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, pin_cfg_value, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-
-		/* read io input data registar */
-		rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_IN_LO__A, &value, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-		if ((value & 0x1000) != 0)	/* check 12th bit - 4th UIO */
-			uio_data->value = true;
-		else
-			uio_data->value = false;
-
-		break;
-      /*====================================================================*/
-	default:
-		return -EINVAL;
-	}			/* switch ( uio_data->uio ) */
-
-	/*  Write magic word to disable pdr reg write               */
-	rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
-	if (rc != 0) {
-		pr_err("error %d\n", rc);
-		goto rw_error;
-	}
-
-	return 0;
-rw_error:
-	return -EIO;
-}
-#endif
-
 /*---------------------------------------------------------------------------*/
 /* UIO Configuration Functions - end                                         */
 /*---------------------------------------------------------------------------*/
@@ -4648,119 +3971,6 @@ rw_error:
 	return -EIO;
 }
 
-#if 0
-/**
-* \fn int ctrl_set_cfg_smart_ant()
-* \brief Set Smart Antenna.
-* \param pointer to struct drxj_cfg_smart_ant.
-* \return int.
-*
-*/
-static int
-ctrl_set_cfg_smart_ant(struct drx_demod_instance *demod, struct drxj_cfg_smart_ant *smart_ant)
-{
-	struct drxj_data *ext_attr = NULL;
-	struct i2c_device_addr *dev_addr = NULL;
-	int rc;
-	u32 start_time = 0;
-	u16 data = 0;
-	static bool bit_inverted;
-
-	dev_addr = demod->my_i2c_dev_addr;
-	ext_attr = (struct drxj_data *) demod->my_ext_attr;
-
-	/* check arguments */
-	if (smart_ant == NULL)
-		return -EINVAL;
-
-	if (bit_inverted != ext_attr->smart_ant_inverted
-	    || ext_attr->uio_sma_tx_mode != DRX_UIO_MODE_FIRMWARE_SMA) {
-		rc = smart_ant_init(demod);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-		bit_inverted = ext_attr->smart_ant_inverted;
-	}
-
-	/*  Write magic word to enable pdr reg write               */
-	rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
-	if (rc != 0) {
-		pr_err("error %d\n", rc);
-		goto rw_error;
-	}
-
-	switch (smart_ant->io) {
-	case DRXJ_SMT_ANT_OUTPUT:
-		/* enable Tx if Mode B (input) is supported */
-		/*
-		   RR16( dev_addr, SIO_SA_TX_COMMAND__A, &data );
-		   WR16( dev_addr, SIO_SA_TX_COMMAND__A, data | SIO_SA_TX_COMMAND_TX_ENABLE__M );
-		 */
-		start_time = jiffies_to_msecs(jiffies);
-		do {
-			rc = drxj_dap_read_reg16(dev_addr, SIO_SA_TX_STATUS__A, &data, 0);
-			if (rc != 0) {
-				pr_err("error %d\n", rc);
-				goto rw_error;
-			}
-		} while ((data & SIO_SA_TX_STATUS_BUSY__M) && ((jiffies_to_msecs(jiffies) - start_time) < DRXJ_MAX_WAITTIME));
-
-		if (data & SIO_SA_TX_STATUS_BUSY__M)
-			return -EIO;
-
-		/* write to smart antenna configuration register */
-		rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_DATA0__A, 0x9200 | ((smart_ant->ctrl_data & 0x0001) << 8) | ((smart_ant->ctrl_data & 0x0002) << 10) | ((smart_ant->ctrl_data & 0x0004) << 12), 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-		rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_DATA1__A, 0x4924 | ((smart_ant->ctrl_data & 0x0008) >> 2) | ((smart_ant->ctrl_data & 0x0010)) | ((smart_ant->ctrl_data & 0x0020) << 2) | ((smart_ant->ctrl_data & 0x0040) << 4) | ((smart_ant->ctrl_data & 0x0080) << 6), 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-		rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_DATA2__A, 0x2492 | ((smart_ant->ctrl_data & 0x0100) >> 8) | ((smart_ant->ctrl_data & 0x0200) >> 6) | ((smart_ant->ctrl_data & 0x0400) >> 4) | ((smart_ant->ctrl_data & 0x0800) >> 2) | ((smart_ant->ctrl_data & 0x1000)) | ((smart_ant->ctrl_data & 0x2000) << 2), 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-		rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_DATA3__A, 0xff8d, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-
-		/* trigger the sending */
-		rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_LENGTH__A, 56, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-
-		break;
-	case DRXJ_SMT_ANT_INPUT:
-		/* disable Tx if Mode B (input) is supported */
-		/*
-		   RR16( dev_addr, SIO_SA_TX_COMMAND__A, &data );
-		   WR16( dev_addr, SIO_SA_TX_COMMAND__A, data & (~SIO_SA_TX_COMMAND_TX_ENABLE__M) );
-		 */
-	default:
-		return -EINVAL;
-	}
-	/*  Write magic word to enable pdr reg write               */
-	rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0);
-	if (rc != 0) {
-		pr_err("error %d\n", rc);
-		goto rw_error;
-	}
-
-	return 0;
-rw_error:
-	return -EIO;
-}
-#endif
-
 static int scu_command(struct i2c_device_addr *dev_addr, struct drxjscu_cmd *cmd)
 {
 	int rc;
@@ -5141,321 +4351,6 @@ rw_error:
 	return -EIO;
 }
 
-#if 0
-/**
-* \brief Configure IQM AF registers
-* \param demod instance of demodulator.
-* \param active
-* \return int.
-*/
-static int iqm_set_af(struct drx_demod_instance *demod, bool active)
-{
-	struct i2c_device_addr *dev_addr = demod->my_i2c_dev_addr;
-	int rc;
-	u16 data = 0;
-
-	/* Configure IQM */
-	rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0);
-	if (rc != 0) {
-		pr_err("error %d\n", rc);
-		goto rw_error;
-	}
-	if (!active)
-		data &= ((~IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_PD_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE) & (~IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE));
-	else
-		data |= (IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE | IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE | IQM_AF_STDBY_STDBY_PD_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE | IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE);
-	rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0);
-	if (rc != 0) {
-		pr_err("error %d\n", rc);
-		goto rw_error;
-	}
-
-	return 0;
-rw_error:
-	return -EIO;
-}
-
-/* -------------------------------------------------------------------------- */
-static int
-ctrl_set_cfg_atv_output(struct drx_demod_instance *demod, struct drxj_cfg_atv_output *output_cfg);
-
-/**
-* \brief set configuration of pin-safe mode
-* \param demod instance of demodulator.
-* \param enable boolean; true: activate pin-safe mode, false: de-activate p.s.m.
-* \return int.
-*/
-static int
-ctrl_set_cfg_pdr_safe_mode(struct drx_demod_instance *demod, bool *enable)
-{
-	struct drxj_data *ext_attr = NULL;
-	struct i2c_device_addr *dev_addr = NULL;
-	int rc;
-
-	if (enable == NULL)
-		return -EINVAL;
-
-	dev_addr = demod->my_i2c_dev_addr;
-	ext_attr = (struct drxj_data *) demod->my_ext_attr;
-
-	/*  Write magic word to enable pdr reg write  */
-	rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0);
-	if (rc != 0) {
-		pr_err("error %d\n", rc);
-		goto rw_error;
-	}
-
-	if (*enable) {
-		bool bridge_enabled = false;
-
-		/* MPEG pins to input */
-		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, DRXJ_PIN_SAFE_MODE, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, DRXJ_PIN_SAFE_MODE, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, DRXJ_PIN_SAFE_MODE, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, DRXJ_PIN_SAFE_MODE, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, DRXJ_PIN_SAFE_MODE, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, DRXJ_PIN_SAFE_MODE, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, DRXJ_PIN_SAFE_MODE, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, DRXJ_PIN_SAFE_MODE, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, DRXJ_PIN_SAFE_MODE, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, DRXJ_PIN_SAFE_MODE, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, DRXJ_PIN_SAFE_MODE, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, DRXJ_PIN_SAFE_MODE, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-
-		/* PD_I2C_SDA2 Bridge off, Port2 Inactive
-		   PD_I2C_SCL2 Bridge off, Port2 Inactive */
-		rc = ctrl_i2c_bridge(demod, &bridge_enabled);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_I2C_SDA2_CFG__A, DRXJ_PIN_SAFE_MODE, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_I2C_SCL2_CFG__A, DRXJ_PIN_SAFE_MODE, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-
-		/*  PD_GPIO     Store and set to input
-		   PD_VSYNC    Store and set to input
-		   PD_SMA_RX   Store and set to input
-		   PD_SMA_TX   Store and set to input */
-		rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_GPIO_CFG__A, &ext_attr->pdr_safe_restore_val_gpio, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-		rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_VSYNC_CFG__A, &ext_attr->pdr_safe_restore_val_v_sync, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-		rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_SMA_RX_CFG__A, &ext_attr->pdr_safe_restore_val_sma_rx, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-		rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_SMA_TX_CFG__A, &ext_attr->pdr_safe_restore_val_sma_tx, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_GPIO_CFG__A, DRXJ_PIN_SAFE_MODE, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_VSYNC_CFG__A, DRXJ_PIN_SAFE_MODE, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_SMA_RX_CFG__A, DRXJ_PIN_SAFE_MODE, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_SMA_TX_CFG__A, DRXJ_PIN_SAFE_MODE, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-
-		/*  PD_RF_AGC   Analog DAC outputs, cannot be set to input or tristate!
-		   PD_IF_AGC   Analog DAC outputs, cannot be set to input or tristate! */
-		rc = iqm_set_af(demod, false);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-
-		/*  PD_CVBS     Analog DAC output, standby mode
-		   PD_SIF      Analog DAC output, standby mode */
-		rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE)), 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-
-		/*  PD_I2S_CL   Input
-		   PD_I2S_DA   Input
-		   PD_I2S_WS   Input */
-		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_I2S_CL_CFG__A, DRXJ_PIN_SAFE_MODE, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_I2S_DA_CFG__A, DRXJ_PIN_SAFE_MODE, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_I2S_WS_CFG__A, DRXJ_PIN_SAFE_MODE, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-	} else {
-		/* No need to restore MPEG pins;
-		   is done in SetStandard/SetChannel */
-
-		/* PD_I2C_SDA2 Port2 active
-		   PD_I2C_SCL2 Port2 active */
-		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_I2C_SDA2_CFG__A, SIO_PDR_I2C_SDA2_CFG__PRE, 0);
-		if (rc != 0) {
-			pr_err("error %d\n", rc);
-			goto rw_error;
-		}
-		rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_I2C_SCL2_CFG__A, SIO_PDR_I2C_SCL2_CFG__PRE, 0);
-		if (rc != 0) {