diff options
| author | Dave Airlie <airlied@gmail.com> | 2013-01-26 18:17:39 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@gmail.com> | 2013-01-26 18:17:39 +1000 |
| commit | 483674325f64a37c7696edb12ce6ad3e535421bc (patch) | |
| tree | b9b334854ad4fa931b211f0f44a47e4d75d3c514 /drivers/iommu | |
| parent | f0f21aa53a30fffd69899794da3a077960f27771 (diff) | |
| parent | 4518f611ba21ba165ea3714055938a8984a44ff9 (diff) | |
Merge branch 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel
Just a few small things:
- 2x workaround bits from Chris to fix up the new scanline waits enabled
in 3.8 on snb. People who've been struck by this on dual-screen also
need to upgrade the ddx.
- Dump the kernel version into i915_error_state, we've had a few mixups
there recently.
- Disable gfx DMAR on gen4 devices, acked by David Woodhouse.
* 'drm-intel-fixes' of git://people.freedesktop.org/~danvet/drm-intel:
drm/i915: dump UTS_RELEASE into the error_state
iommu/intel: disable DMAR for g4x integrated gfx
drm/i915: GFX_MODE Flush TLB Invalidate Mode must be '1' for scanline waits
drm/i915: Disable AsyncFlip performance optimisations
Diffstat (limited to 'drivers/iommu')
| -rw-r--r-- | drivers/iommu/intel-iommu.c | 21 |
1 files changed, 15 insertions, 6 deletions
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c index b9d091157884..eca28014ef3e 100644 --- a/drivers/iommu/intel-iommu.c +++ b/drivers/iommu/intel-iommu.c @@ -4234,6 +4234,21 @@ static struct iommu_ops intel_iommu_ops = { .pgsize_bitmap = INTEL_IOMMU_PGSIZES, }; +static void quirk_iommu_g4x_gfx(struct pci_dev *dev) +{ + /* G4x/GM45 integrated gfx dmar support is totally busted. */ + printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n"); + dmar_map_gfx = 0; +} + +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_g4x_gfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_g4x_gfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_g4x_gfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_g4x_gfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_g4x_gfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_g4x_gfx); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_g4x_gfx); + static void quirk_iommu_rwbf(struct pci_dev *dev) { /* @@ -4242,12 +4257,6 @@ static void quirk_iommu_rwbf(struct pci_dev *dev) */ printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n"); rwbf_quirk = 1; - - /* https://bugzilla.redhat.com/show_bug.cgi?id=538163 */ - if (dev->revision == 0x07) { - printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n"); - dmar_map_gfx = 0; - } } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf); |