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authorVince Hsu <vinceh@nvidia.com>2014-12-22 17:11:39 +0800
committerBen Skeggs <bskeggs@redhat.com>2015-01-22 12:15:04 +1000
commit9f7fd620af29d4501ed063333824562656d46da5 (patch)
tree98583738d76273a99bdd89ccfd2adf6339839df7 /drivers/gpu/drm/nouveau/core/include/subdev/pwr.h
parent47e7df39d9fb74fa11bd4b4453fc34d231b2169c (diff)
drm/nouveau/pwr: add support for GK20A
This patch adds PWR support for GK20A. But instead of adding the PWR features like firmware loading and communication with PMU firmware, we add the DVFS (Dynamic Voltage and Frequency Scaling), which is one of the PMU firmware's jobs on dGPUs, in this patch. This refers to the idle signals provided by the NVIDIA hardware and tries to adjust the performance level based on the calculated target. The reclocking policy can be fine-tuned later when we have more real use cases. Signed-off-by: Vince Hsu <vinceh@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/core/include/subdev/pwr.h')
-rw-r--r--drivers/gpu/drm/nouveau/core/include/subdev/pwr.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h b/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h
index ef57c85405ff..83f85ac153ef 100644
--- a/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h
+++ b/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h
@@ -38,6 +38,7 @@ extern struct nouveau_oclass *nvc0_pwr_oclass;
extern struct nouveau_oclass *nvd0_pwr_oclass;
extern struct nouveau_oclass *gk104_pwr_oclass;
extern struct nouveau_oclass *nv108_pwr_oclass;
+extern struct nouveau_oclass *gk20a_pwr_oclass;
/* interface to MEMX process running on PPWR */
struct nouveau_memx;