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author | Mauro Carvalho Chehab <mchehab+samsung@kernel.org> | 2018-12-17 10:34:24 -0500 |
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committer | Mauro Carvalho Chehab <mchehab+samsung@kernel.org> | 2018-12-17 10:34:24 -0500 |
commit | 4bd257d884902b81493cf11531915009ab5787cf (patch) | |
tree | bf60af2fb9454154e30b888f7f86a9845ad2c4b7 /drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | |
parent | d2b4387f3bdf016e266d23cf657465f557721488 (diff) | |
parent | 7566ec393f4161572ba6f11ad5171fd5d59b0fbd (diff) |
Merge tag 'v4.20-rc7' into patchwork
Linux 4.20-rc7
* tag 'v4.20-rc7': (403 commits)
Linux 4.20-rc7
scripts/spdxcheck.py: always open files in binary mode
checkstack.pl: fix for aarch64
userfaultfd: check VM_MAYWRITE was set after verifying the uffd is registered
fs/iomap.c: get/put the page in iomap_page_create/release()
hugetlbfs: call VM_BUG_ON_PAGE earlier in free_huge_page()
memblock: annotate memblock_is_reserved() with __init_memblock
psi: fix reference to kernel commandline enable
arch/sh/include/asm/io.h: provide prototypes for PCI I/O mapping in asm/io.h
mm/sparse: add common helper to mark all memblocks present
mm: introduce common STRUCT_PAGE_MAX_SHIFT define
alpha: fix hang caused by the bootmem removal
XArray: Fix xa_alloc when id exceeds max
drm/vmwgfx: Protect from excessive execbuf kernel memory allocations v3
MAINTAINERS: Daniel for drm co-maintainer
drm/amdgpu: drop fclk/gfxclk ratio setting
IB/core: Fix oops in netdev_next_upper_dev_rcu()
dm thin: bump target version
drm/vmwgfx: remove redundant return ret statement
drm/i915: Flush GPU relocs harder for gen3
...
Diffstat (limited to 'drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c')
-rw-r--r-- | drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c index 4c03f0b7343e..41bec570c518 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c @@ -39,6 +39,8 @@ #define DSI_PIXEL_PLL_CLK 1 #define NUM_PROVIDED_CLKS 2 +#define VCO_REF_CLK_RATE 19200000 + struct dsi_pll_regs { u32 pll_prop_gain_rate; u32 pll_lockdet_rate; @@ -316,7 +318,7 @@ static int dsi_pll_10nm_vco_set_rate(struct clk_hw *hw, unsigned long rate, parent_rate); pll_10nm->vco_current_rate = rate; - pll_10nm->vco_ref_clk_rate = parent_rate; + pll_10nm->vco_ref_clk_rate = VCO_REF_CLK_RATE; dsi_pll_setup_config(pll_10nm); |