diff options
author | Chiawen Huang <chiawen.huang@amd.com> | 2020-07-02 06:47:05 +0800 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2020-07-14 14:34:08 -0400 |
commit | 1bdcc35f7767988d49e55c6e44b80da666067f8b (patch) | |
tree | 4fae621779bb671d6ac581cd786436f1887ee87c /drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h | |
parent | ca751df231d14fd2bd1f8ee700d6a16cc541706a (diff) |
drm/amd/display: reduce sr_xxx_time by 3 us when ppt disable
[Why]
when ppt disabled, the watermark doesn't get fine tune causing
underflow.
[How]
It is a temporary solution to reduce sr_xxx_time by 3 us when ppt
disable.
Signed-off-by: Chiawen Huang <chiawen.huang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h')
-rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h index b3b8b46d293e..4e6e18bbef5d 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h @@ -270,6 +270,7 @@ struct clk_mgr_internal { enum dm_pp_clocks_state max_clks_state; enum dm_pp_clocks_state cur_min_clks_state; + bool periodic_retraining_disabled; unsigned int cur_phyclk_req_table[MAX_PIPES * 2]; #ifdef CONFIG_DRM_AMD_DC_DCN3_0 |