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authorMurton Liu <murton.liu@amd.com>2019-06-24 11:28:06 -0400
committerAlex Deucher <alexander.deucher@amd.com>2019-07-18 14:27:24 -0500
commitd40605b6d088b20827e442903022c65f0f165c84 (patch)
treeb533b80a40f5c60494f2b66a61a2c132e19eeee7 /drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
parent4c6a9618076c2690a361e8bc32549720f2f42305 (diff)
drm/amd/display: Implement generic MUX registers (v2)
[Why] Logic & structures for generic regs does not exist in DC currently. [How] Implement register masks/shifts and relevant functions for generic mux, similar to existing HPD and DDC objects. V2: fix includes for kalloc/free (Alex) Signed-off-by: Murton Liu <murton.liu@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Joshua Aberback <Joshua.Aberback@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c')
-rw-r--r--drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c41
1 files changed, 39 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
index abd76d855375..afb7c0f111bf 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
@@ -31,6 +31,7 @@
#include "../hw_gpio.h"
#include "../hw_ddc.h"
#include "../hw_hpd.h"
+#include "../hw_generic.h"
#include "hw_factory_dcn20.h"
@@ -138,6 +139,32 @@ static const struct ddc_sh_mask ddc_mask[] = {
DDC_MASK_SH_LIST_DCN2(_MASK, 6)
};
+#include "../generic_regs.h"
+
+/* set field name */
+#define SF_GENERIC(reg_name, field_name, post_fix)\
+ .field_name = reg_name ## __ ## field_name ## post_fix
+
+#define generic_regs(id) \
+{\
+ GENERIC_REG_LIST(id)\
+}
+
+static const struct generic_registers generic_regs[] = {
+ generic_regs(A),
+ generic_regs(B),
+};
+
+static const struct generic_sh_mask generic_shift[] = {
+ GENERIC_MASK_SH_LIST(__SHIFT, A),
+ GENERIC_MASK_SH_LIST(__SHIFT, B),
+};
+
+static const struct generic_sh_mask generic_mask[] = {
+ GENERIC_MASK_SH_LIST(_MASK, A),
+ GENERIC_MASK_SH_LIST(_MASK, B),
+};
+
static void define_ddc_registers(
struct hw_gpio_pin *pin,
uint32_t en)
@@ -173,17 +200,27 @@ static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
hpd->base.regs = &hpd_regs[en].gpio;
}
+static void define_generic_registers(struct hw_gpio_pin *pin, uint32_t en)
+{
+ struct hw_generic *generic = HW_GENERIC_FROM_BASE(pin);
+
+ generic->regs = &generic_regs[en];
+ generic->shifts = &generic_shift[en];
+ generic->masks = &generic_mask[en];
+ generic->base.regs = &generic_regs[en].gpio;
+}
/* fucntion table */
static const struct hw_factory_funcs funcs = {
.create_ddc_data = dal_hw_ddc_create,
.create_ddc_clock = dal_hw_ddc_create,
- .create_generic = NULL,
+ .create_generic = dal_hw_generic_create,
.create_hpd = dal_hw_hpd_create,
.create_sync = NULL,
.create_gsl = NULL,
.define_hpd_registers = define_hpd_registers,
- .define_ddc_registers = define_ddc_registers
+ .define_ddc_registers = define_ddc_registers,
+ .define_generic_registers = define_generic_registers,
};
/*
* dal_hw_factory_dcn10_init