diff options
| author | hersen wu <hersenxs.wu@amd.com> | 2019-03-13 16:21:26 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-06-22 09:34:08 -0500 |
| commit | 9e14d4f17e23ce46d346a6a22a295b4a65b9d918 (patch) | |
| tree | fafa728e538b8121b7904e922f3046b647171ede /drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | |
| parent | 0fcf90d1775e09fbee2afe40a43f6400c103ac55 (diff) | |
drm/amd/display: skip dsc config for navi10 bring up
[why] we meet a bug when program dsc register even dsc mode is not
enabled. disable dsc config for now. we will re-visit this issue.
Signed-off-by: hersen wu <hersenxs.wu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c index 724b5a9e47d0..34f5a7d671b2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c @@ -191,6 +191,15 @@ void optc2_set_dsc_config(struct timing_generator *optc, uint32_t dsc_slice_width) { struct optc *optc1 = DCN10TG_FROM_TG(optc); + uint32_t data_format = 0; + /* skip if dsc mode is not changed */ + data_format = dm_read_reg(CTX, REG(OPTC_DATA_FORMAT_CONTROL)); + + data_format = data_format & 0x30; /* bit5:4 */ + data_format = data_format >> 4; + + if (data_format == dsc_mode) + return; REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, OPTC_DSC_MODE, dsc_mode); |