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authorChristian König <christian.koenig@amd.com>2020-04-01 11:18:21 +0200
committerAlex Deucher <alexander.deucher@amd.com>2020-04-28 16:20:30 -0400
commit9ecefb19c3a6626c27ea7ee72d431f22462e1d54 (patch)
tree5a05fd5a5db49a9d7579bb30ea81c13a62f46003 /drivers/gpu/drm/amd/amdgpu/amdgpu.h
parente208586471181230b88851c14cac80036c128f37 (diff)
drm/amdgpu: cleanup IB pool handling a bit
Fix the coding style, move and rename the definitions to better match what they are supposed to be doing. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu.h')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h11
1 files changed, 1 insertions, 10 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 589d8783fa21..99e5f474505d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -204,8 +204,6 @@ extern int amdgpu_cik_support;
#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
-/* AMDGPU_IB_POOL_SIZE must be a power of 2 */
-#define AMDGPU_IB_POOL_SIZE 16
#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
#define AMDGPUFB_CONN_LIMIT 4
#define AMDGPU_BIOS_NUM_SCRATCH 16
@@ -402,13 +400,6 @@ struct amdgpu_sa_bo {
int amdgpu_fence_slab_init(void);
void amdgpu_fence_slab_fini(void);
-enum amdgpu_ib_pool_type {
- AMDGPU_IB_POOL_NORMAL = 0,
- AMDGPU_IB_POOL_VM,
- AMDGPU_IB_POOL_DIRECT,
-
- AMDGPU_IB_POOL_MAX
-};
/*
* IRQS.
*/
@@ -866,7 +857,7 @@ struct amdgpu_device {
unsigned num_rings;
struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
bool ib_pool_ready;
- struct amdgpu_sa_manager ring_tmp_bo[AMDGPU_IB_POOL_MAX];
+ struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX];
struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX];
/* interrupts */