dmaengine: ti: New directory for Texas Instruments DMA drivers

Collect the Texas Instruments DMA drivers under drivers/dma/ti/

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>

1 files changed, 0 insertions, 2568 deletions

diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
deleted file mode 100644
index 85ea92fcea54..000000000000
--- a/drivers/dma/edma.c
+++ /dev/null
@@ -1,2568 +0,0 @@
-/*
- * TI EDMA DMA engine driver
- *
- * Copyright 2012 Texas Instruments
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/dmaengine.h>
-#include <linux/dma-mapping.h>
-#include <linux/edma.h>
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-#include <linux/spinlock.h>
-#include <linux/of.h>
-#include <linux/of_dma.h>
-#include <linux/of_irq.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/pm_runtime.h>
-
-#include <linux/platform_data/edma.h>
-
-#include "dmaengine.h"
-#include "virt-dma.h"
-
-/* Offsets matching "struct edmacc_param" */
-#define PARM_OPT		0x00
-#define PARM_SRC		0x04
-#define PARM_A_B_CNT		0x08
-#define PARM_DST		0x0c
-#define PARM_SRC_DST_BIDX	0x10
-#define PARM_LINK_BCNTRLD	0x14
-#define PARM_SRC_DST_CIDX	0x18
-#define PARM_CCNT		0x1c
-
-#define PARM_SIZE		0x20
-
-/* Offsets for EDMA CC global channel registers and their shadows */
-#define SH_ER			0x00	/* 64 bits */
-#define SH_ECR			0x08	/* 64 bits */
-#define SH_ESR			0x10	/* 64 bits */
-#define SH_CER			0x18	/* 64 bits */
-#define SH_EER			0x20	/* 64 bits */
-#define SH_EECR			0x28	/* 64 bits */
-#define SH_EESR			0x30	/* 64 bits */
-#define SH_SER			0x38	/* 64 bits */
-#define SH_SECR			0x40	/* 64 bits */
-#define SH_IER			0x50	/* 64 bits */
-#define SH_IECR			0x58	/* 64 bits */
-#define SH_IESR			0x60	/* 64 bits */
-#define SH_IPR			0x68	/* 64 bits */
-#define SH_ICR			0x70	/* 64 bits */
-#define SH_IEVAL		0x78
-#define SH_QER			0x80
-#define SH_QEER			0x84
-#define SH_QEECR		0x88
-#define SH_QEESR		0x8c
-#define SH_QSER			0x90
-#define SH_QSECR		0x94
-#define SH_SIZE			0x200
-
-/* Offsets for EDMA CC global registers */
-#define EDMA_REV		0x0000
-#define EDMA_CCCFG		0x0004
-#define EDMA_QCHMAP		0x0200	/* 8 registers */
-#define EDMA_DMAQNUM		0x0240	/* 8 registers (4 on OMAP-L1xx) */
-#define EDMA_QDMAQNUM		0x0260
-#define EDMA_QUETCMAP		0x0280
-#define EDMA_QUEPRI		0x0284
-#define EDMA_EMR		0x0300	/* 64 bits */
-#define EDMA_EMCR		0x0308	/* 64 bits */
-#define EDMA_QEMR		0x0310
-#define EDMA_QEMCR		0x0314
-#define EDMA_CCERR		0x0318
-#define EDMA_CCERRCLR		0x031c
-#define EDMA_EEVAL		0x0320
-#define EDMA_DRAE		0x0340	/* 4 x 64 bits*/
-#define EDMA_QRAE		0x0380	/* 4 registers */
-#define EDMA_QUEEVTENTRY	0x0400	/* 2 x 16 registers */
-#define EDMA_QSTAT		0x0600	/* 2 registers */
-#define EDMA_QWMTHRA		0x0620
-#define EDMA_QWMTHRB		0x0624
-#define EDMA_CCSTAT		0x0640
-
-#define EDMA_M			0x1000	/* global channel registers */
-#define EDMA_ECR		0x1008
-#define EDMA_ECRH		0x100C
-#define EDMA_SHADOW0		0x2000	/* 4 shadow regions */
-#define EDMA_PARM		0x4000	/* PaRAM entries */
-
-#define PARM_OFFSET(param_no)	(EDMA_PARM + ((param_no) << 5))
-
-#define EDMA_DCHMAP		0x0100  /* 64 registers */
-
-/* CCCFG register */
-#define GET_NUM_DMACH(x)	(x & 0x7) /* bits 0-2 */
-#define GET_NUM_QDMACH(x)	((x & 0x70) >> 4) /* bits 4-6 */
-#define GET_NUM_PAENTRY(x)	((x & 0x7000) >> 12) /* bits 12-14 */
-#define GET_NUM_EVQUE(x)	((x & 0x70000) >> 16) /* bits 16-18 */
-#define GET_NUM_REGN(x)		((x & 0x300000) >> 20) /* bits 20-21 */
-#define CHMAP_EXIST		BIT(24)
-
-/* CCSTAT register */
-#define EDMA_CCSTAT_ACTV	BIT(4)
-
-/*
- * Max of 20 segments per channel to conserve PaRAM slots
- * Also note that MAX_NR_SG should be atleast the no.of periods
- * that are required for ASoC, otherwise DMA prep calls will
- * fail. Today davinci-pcm is the only user of this driver and
- * requires atleast 17 slots, so we setup the default to 20.
- */
-#define MAX_NR_SG		20
-#define EDMA_MAX_SLOTS		MAX_NR_SG
-#define EDMA_DESCRIPTORS	16
-
-#define EDMA_CHANNEL_ANY		-1	/* for edma_alloc_channel() */
-#define EDMA_SLOT_ANY			-1	/* for edma_alloc_slot() */
-#define EDMA_CONT_PARAMS_ANY		 1001
-#define EDMA_CONT_PARAMS_FIXED_EXACT	 1002
-#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
-
-/* PaRAM slots are laid out like this */
-struct edmacc_param {
-	u32 opt;
-	u32 src;
-	u32 a_b_cnt;
-	u32 dst;
-	u32 src_dst_bidx;
-	u32 link_bcntrld;
-	u32 src_dst_cidx;
-	u32 ccnt;
-} __packed;
-
-/* fields in edmacc_param.opt */
-#define SAM		BIT(0)
-#define DAM		BIT(1)
-#define SYNCDIM		BIT(2)
-#define STATIC		BIT(3)
-#define EDMA_FWID	(0x07 << 8)
-#define TCCMODE		BIT(11)
-#define EDMA_TCC(t)	((t) << 12)
-#define TCINTEN		BIT(20)
-#define ITCINTEN	BIT(21)
-#define TCCHEN		BIT(22)
-#define ITCCHEN		BIT(23)
-
-struct edma_pset {
-	u32				len;
-	dma_addr_t			addr;
-	struct edmacc_param		param;
-};
-
-struct edma_desc {
-	struct virt_dma_desc		vdesc;
-	struct list_head		node;
-	enum dma_transfer_direction	direction;
-	int				cyclic;
-	int				absync;
-	int				pset_nr;
-	struct edma_chan		*echan;
-	int				processed;
-
-	/*
-	 * The following 4 elements are used for residue accounting.
-	 *
-	 * - processed_stat: the number of SG elements we have traversed
-	 * so far to cover accounting. This is updated directly to processed
-	 * during edma_callback and is always <= processed, because processed
-	 * refers to the number of pending transfer (programmed to EDMA
-	 * controller), where as processed_stat tracks number of transfers
-	 * accounted for so far.
-	 *
-	 * - residue: The amount of bytes we have left to transfer for this desc
-	 *
-	 * - residue_stat: The residue in bytes of data we have covered
-	 * so far for accounting. This is updated directly to residue
-	 * during callbacks to keep it current.
-	 *
-	 * - sg_len: Tracks the length of the current intermediate transfer,
-	 * this is required to update the residue during intermediate transfer
-	 * completion callback.
-	 */
-	int				processed_stat;
-	u32				sg_len;
-	u32				residue;
-	u32				residue_stat;
-
-	struct edma_pset		pset[0];
-};
-
-struct edma_cc;
-
-struct edma_tc {
-	struct device_node		*node;
-	u16				id;
-};
-
-struct edma_chan {
-	struct virt_dma_chan		vchan;
-	struct list_head		node;
-	struct edma_desc		*edesc;
-	struct edma_cc			*ecc;
-	struct edma_tc			*tc;
-	int				ch_num;
-	bool				alloced;
-	bool				hw_triggered;
-	int				slot[EDMA_MAX_SLOTS];
-	int				missed;
-	struct dma_slave_config		cfg;
-};
-
-struct edma_cc {
-	struct device			*dev;
-	struct edma_soc_info		*info;
-	void __iomem			*base;
-	int				id;
-	bool				legacy_mode;
-
-	/* eDMA3 resource information */
-	unsigned			num_channels;
-	unsigned			num_qchannels;
-	unsigned			num_region;
-	unsigned			num_slots;
-	unsigned			num_tc;
-	bool				chmap_exist;
-	enum dma_event_q		default_queue;
-
-	unsigned int			ccint;
-	unsigned int			ccerrint;
-
-	/*
-	 * The slot_inuse bit for each PaRAM slot is clear unless the slot is
-	 * in use by Linux or if it is allocated to be used by DSP.
-	 */
-	unsigned long *slot_inuse;
-
-	struct dma_device		dma_slave;
-	struct dma_device		*dma_memcpy;
-	struct edma_chan		*slave_chans;
-	struct edma_tc			*tc_list;
-	int				dummy_slot;
-};
-
-/* dummy param set used to (re)initialize parameter RAM slots */
-static const struct edmacc_param dummy_paramset = {
-	.link_bcntrld = 0xffff,
-	.ccnt = 1,
-};
-
-#define EDMA_BINDING_LEGACY	0
-#define EDMA_BINDING_TPCC	1
-static const u32 edma_binding_type[] = {
-	[EDMA_BINDING_LEGACY] = EDMA_BINDING_LEGACY,
-	[EDMA_BINDING_TPCC] = EDMA_BINDING_TPCC,
-};
-
-static const struct of_device_id edma_of_ids[] = {
-	{
-		.compatible = "ti,edma3",
-		.data = &edma_binding_type[EDMA_BINDING_LEGACY],
-	},
-	{
-		.compatible = "ti,edma3-tpcc",
-		.data = &edma_binding_type[EDMA_BINDING_TPCC],
-	},
-	{}
-};
-MODULE_DEVICE_TABLE(of, edma_of_ids);
-
-static const struct of_device_id edma_tptc_of_ids[] = {
-	{ .compatible = "ti,edma3-tptc", },
-	{}
-};
-MODULE_DEVICE_TABLE(of, edma_tptc_of_ids);
-
-static inline unsigned int edma_read(struct edma_cc *ecc, int offset)
-{
-	return (unsigned int)__raw_readl(ecc->base + offset);
-}
-
-static inline void edma_write(struct edma_cc *ecc, int offset, int val)
-{
-	__raw_writel(val, ecc->base + offset);
-}
-
-static inline void edma_modify(struct edma_cc *ecc, int offset, unsigned and,
-			       unsigned or)
-{
-	unsigned val = edma_read(ecc, offset);
-
-	val &= and;
-	val |= or;
-	edma_write(ecc, offset, val);
-}
-
-static inline void edma_and(struct edma_cc *ecc, int offset, unsigned and)
-{
-	unsigned val = edma_read(ecc, offset);
-
-	val &= and;
-	edma_write(ecc, offset, val);
-}
-
-static inline void edma_or(struct edma_cc *ecc, int offset, unsigned or)
-{
-	unsigned val = edma_read(ecc, offset);
-
-	val |= or;
-	edma_write(ecc, offset, val);
-}
-
-static inline unsigned int edma_read_array(struct edma_cc *ecc, int offset,
-					   int i)
-{
-	return edma_read(ecc, offset + (i << 2));
-}
-
-static inline void edma_write_array(struct edma_cc *ecc, int offset, int i,
-				    unsigned val)
-{
-	edma_write(ecc, offset + (i << 2), val);
-}
-
-static inline void edma_modify_array(struct edma_cc *ecc, int offset, int i,
-				     unsigned and, unsigned or)
-{
-	edma_modify(ecc, offset + (i << 2), and, or);
-}
-
-static inline void edma_or_array(struct edma_cc *ecc, int offset, int i,
-				 unsigned or)
-{
-	edma_or(ecc, offset + (i << 2), or);
-}
-
-static inline void edma_or_array2(struct edma_cc *ecc, int offset, int i, int j,
-				  unsigned or)
-{
-	edma_or(ecc, offset + ((i * 2 + j) << 2), or);
-}
-
-static inline void edma_write_array2(struct edma_cc *ecc, int offset, int i,
-				     int j, unsigned val)
-{
-	edma_write(ecc, offset + ((i * 2 + j) << 2), val);
-}
-
-static inline unsigned int edma_shadow0_read(struct edma_cc *ecc, int offset)
-{
-	return edma_read(ecc, EDMA_SHADOW0 + offset);
-}
-
-static inline unsigned int edma_shadow0_read_array(struct edma_cc *ecc,
-						   int offset, int i)
-{
-	return edma_read(ecc, EDMA_SHADOW0 + offset + (i << 2));
-}
-
-static inline void edma_shadow0_write(struct edma_cc *ecc, int offset,
-				      unsigned val)
-{
-	edma_write(ecc, EDMA_SHADOW0 + offset, val);
-}
-
-static inline void edma_shadow0_write_array(struct edma_cc *ecc, int offset,
-					    int i, unsigned val)
-{
-	edma_write(ecc, EDMA_SHADOW0 + offset + (i << 2), val);
-}
-
-static inline unsigned int edma_param_read(struct edma_cc *ecc, int offset,
-					   int param_no)
-{
-	return edma_read(ecc, EDMA_PARM + offset + (param_no << 5));
-}
-
-static inline void edma_param_write(struct edma_cc *ecc, int offset,
-				    int param_no, unsigned val)
-{
-	edma_write(ecc, EDMA_PARM + offset + (param_no << 5), val);
-}
-
-static inline void edma_param_modify(struct edma_cc *ecc, int offset,
-				     int param_no, unsigned and, unsigned or)
-{
-	edma_modify(ecc, EDMA_PARM + offset + (param_no << 5), and, or);
-}
-
-static inline void edma_param_and(struct edma_cc *ecc, int offset, int param_no,
-				  unsigned and)
-{
-	edma_and(ecc, EDMA_PARM + offset + (param_no << 5), and);
-}
-
-static inline void edma_param_or(struct edma_cc *ecc, int offset, int param_no,
-				 unsigned or)
-{
-	edma_or(ecc, EDMA_PARM + offset + (param_no << 5), or);
-}
-
-static inline void edma_set_bits(int offset, int len, unsigned long *p)
-{
-	for (; len > 0; len--)
-		set_bit(offset + (len - 1), p);
-}
-
-static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no,
-					  int priority)
-{
-	int bit = queue_no * 4;
-
-	edma_modify(ecc, EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit));
-}
-
-static void edma_set_chmap(struct edma_chan *echan, int slot)
-{
-	struct edma_cc *ecc = echan->ecc;
-	int channel = EDMA_CHAN_SLOT(echan->ch_num);
-
-	if (ecc->chmap_exist) {
-		slot = EDMA_CHAN_SLOT(slot);
-		edma_write_array(ecc, EDMA_DCHMAP, channel, (slot << 5));
-	}
-}
-
-static void edma_setup_interrupt(struct edma_chan *echan, bool enable)
-{
-	struct edma_cc *ecc = echan->ecc;
-	int channel = EDMA_CHAN_SLOT(echan->ch_num);
-
-	if (enable) {
-		edma_shadow0_write_array(ecc, SH_ICR, channel >> 5,
-					 BIT(channel & 0x1f));
-		edma_shadow0_write_array(ecc, SH_IESR, channel >> 5,
-					 BIT(channel & 0x1f));
-	} else {
-		edma_shadow0_write_array(ecc, SH_IECR, channel >> 5,
-					 BIT(channel & 0x1f));
-	}
-}
-
-/*
- * paRAM slot management functions
- */
-static void edma_write_slot(struct edma_cc *ecc, unsigned slot,
-			    const struct edmacc_param *param)
-{
-	slot = EDMA_CHAN_SLOT(slot);
-	if (slot >= ecc->num_slots)
-		return;
-	memcpy_toio(ecc->base + PARM_OFFSET(slot), param, PARM_SIZE);
-}
-
-static int edma_read_slot(struct edma_cc *ecc, unsigned slot,
-			   struct edmacc_param *param)
-{
-	slot = EDMA_CHAN_SLOT(slot);
-	if (slot >= ecc->num_slots)
-		return -EINVAL;
-	memcpy_fromio(param, ecc->base + PARM_OFFSET(slot), PARM_SIZE);
-
-	return 0;
-}
-
-/**
- * edma_alloc_slot - allocate DMA parameter RAM
- * @ecc: pointer to edma_cc struct
- * @slot: specific slot to allocate; negative for "any unused slot"
- *
- * This allocates a parameter RAM slot, initializing it to hold a
- * dummy transfer.  Slots allocated using this routine have not been
- * mapped to a hardware DMA channel, and will normally be used by
- * linking to them from a slot associated with a DMA channel.
- *
- * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
- * slots may be allocated on behalf of DSP firmware.
- *
- * Returns the number of the slot, else negative errno.
- */
-static int edma_alloc_slot(struct edma_cc *ecc, int slot)
-{
-	if (slot >= 0) {
-		slot = EDMA_CHAN_SLOT(slot);
-		/* Requesting entry paRAM slot for a HW triggered channel. */
-		if (ecc->chmap_exist && slot < ecc->num_channels)
-			slot = EDMA_SLOT_ANY;
-	}
-
-	if (slot < 0) {
-		if (ecc->chmap_exist)
-			slot = 0;
-		else
-			slot = ecc->num_channels;
-		for (;;) {
-			slot = find_next_zero_bit(ecc->slot_inuse,
-						  ecc->num_slots,
-						  slot);
-			if (slot == ecc->num_slots)
-				return -ENOMEM;
-			if (!test_and_set_bit(slot, ecc->slot_inuse))
-				break;
-		}
-	} else if (slot >= ecc->num_slots) {
-		return -EINVAL;
-	} else if (test_and_set_bit(slot, ecc->slot_inuse)) {
-		return -EBUSY;
-	}
-
-	edma_write_slot(ecc, slot, &dummy_paramset);
-
-	return EDMA_CTLR_CHAN(ecc->id, slot);
-}
-
-static void edma_free_slot(struct edma_cc *ecc, unsigned slot)
-{
-	slot = EDMA_CHAN_SLOT(slot);
-	if (slot >= ecc->num_slots)
-		return;
-
-	edma_write_slot(ecc, slot, &dummy_paramset);
-	clear_bit(slot, ecc->slot_inuse);
-}
-
-/**
- * edma_link - link one parameter RAM slot to another
- * @ecc: pointer to edma_cc struct
- * @from: parameter RAM slot originating the link
- * @to: parameter RAM slot which is the link target
- *
- * The originating slot should not be part of any active DMA transfer.
- */
-static void edma_link(struct edma_cc *ecc, unsigned from, unsigned to)
-{
-	if (unlikely(EDMA_CTLR(from) != EDMA_CTLR(to)))
-		dev_warn(ecc->dev, "Ignoring eDMA instance for linking\n");
-
-	from = EDMA_CHAN_SLOT(from);
-	to = EDMA_CHAN_SLOT(to);
-	if (from >= ecc->num_slots || to >= ecc->num_slots)
-		return;
-
-	edma_param_modify(ecc, PARM_LINK_BCNTRLD, from, 0xffff0000,
-			  PARM_OFFSET(to));
-}
-
-/**
- * edma_get_position - returns the current transfer point
- * @ecc: pointer to edma_cc struct
- * @slot: parameter RAM slot being examined
- * @dst:  true selects the dest position, false the source
- *
- * Returns the position of the current active slot
- */
-static dma_addr_t edma_get_position(struct edma_cc *ecc, unsigned slot,
-				    bool dst)
-{
-	u32 offs;
-
-	slot = EDMA_CHAN_SLOT(slot);
-	offs = PARM_OFFSET(slot);
-	offs += dst ? PARM_DST : PARM_SRC;
-
-	return edma_read(ecc, offs);
-}
-
-/*
- * Channels with event associations will be triggered by their hardware
- * events, and channels without such associations will be triggered by
- * software.  (At this writing there is no interface for using software
- * triggers except with channels that don't support hardware triggers.)
- */
-static void edma_start(struct edma_chan *echan)
-{
-	struct edma_cc *ecc = echan->ecc;
-	int channel = EDMA_CHAN_SLOT(echan->ch_num);
-	int j = (channel >> 5);
-	unsigned int mask = BIT(channel & 0x1f);
-
-	if (!echan->hw_triggered) {
-		/* EDMA channels without event association */
-		dev_dbg(ecc->dev, "ESR%d %08x\n", j,
-			edma_shadow0_read_array(ecc, SH_ESR, j));
-		edma_shadow0_write_array(ecc, SH_ESR, j, mask);
-	} else {
-		/* EDMA channel with event association */
-		dev_dbg(ecc->dev, "ER%d %08x\n", j,
-			edma_shadow0_read_array(ecc, SH_ER, j));
-		/* Clear any pending event or error */
-		edma_write_array(ecc, EDMA_ECR, j, mask);
-		edma_write_array(ecc, EDMA_EMCR, j, mask);
-		/* Clear any SER */
-		edma_shadow0_write_array(ecc, SH_SECR, j, mask);
-		edma_shadow0_write_array(ecc, SH_EESR, j, mask);
-		dev_dbg(ecc->dev, "EER%d %08x\n", j,
-			edma_shadow0_read_array(ecc, SH_EER, j));
-	}
-}
-
-static void edma_stop(struct edma_chan *echan)
-{
-	struct edma_cc *ecc = echan->ecc;
-	int channel = EDMA_CHAN_SLOT(echan->ch_num);
-	int j = (channel >> 5);
-	unsigned int mask = BIT(channel & 0x1f);
-
-	edma_shadow0_write_array(ecc, SH_EECR, j, mask);
-	edma_shadow0_write_array(ecc, SH_ECR, j, mask);
-	edma_shadow0_write_array(ecc, SH_SECR, j, mask);
-	edma_write_array(ecc, EDMA_EMCR, j, mask);
-
-	/* clear possibly pending completion interrupt */
-	edma_shadow0_write_array(ecc, SH_ICR, j, mask);
-
-	dev_dbg(ecc->dev, "EER%d %08x\n", j,
-		edma_shadow0_read_array(ecc, SH_EER, j));
-
-	/* REVISIT:  consider guarding against inappropriate event
-	 * chaining by overwriting with dummy_paramset.
-	 */
-}
-
-/*
- * Temporarily disable EDMA hardware events on the specified channel,
- * preventing them from triggering new transfers
- */
-static void edma_pause(struct edma_chan *echan)
-{
-	int channel = EDMA_CHAN_SLOT(echan->ch_num);
-	unsigned int mask = BIT(channel & 0x1f);
-
-	edma_shadow0_write_array(echan->ecc, SH_EECR, channel >> 5, mask);
-}
-
-/* Re-enable EDMA hardware events on the specified channel.  */
-static void edma_resume(struct edma_chan *echan)
-{
-	int channel = EDMA_CHAN_SLOT(echan->ch_num);
-	unsigned int mask = BIT(channel & 0x1f);
-
-	edma_shadow0_write_array(echan->ecc, SH_EESR, channel >> 5, mask);
-}
-
-static void edma_trigger_channel(struct edma_chan *echan)
-{
-	struct edma_cc *ecc = echan->ecc;
-	int channel = EDMA_CHAN_SLOT(echan->ch_num);
-	unsigned int mask = BIT(channel & 0x1f);
-
-	edma_shadow0_write_array(ecc, SH_ESR, (channel >> 5), mask);
-
-	dev_dbg(ecc->dev, "ESR%d %08x\n", (channel >> 5),
-		edma_shadow0_read_array(ecc, SH_ESR, (channel >> 5)));
-}
-
-static void edma_clean_channel(struct edma_chan *echan)
-{
-	struct edma_cc *ecc = echan->ecc;
-	int channel = EDMA_CHAN_SLOT(echan->ch_num);
-	int j = (channel >> 5);
-	unsigned int mask = BIT(channel & 0x1f);
-
-	dev_dbg(ecc->dev, "EMR%d %08x\n", j, edma_read_array(ecc, EDMA_EMR, j));
-	edma_shadow0_write_array(ecc, SH_ECR, j, mask);
-	/* Clear the corresponding EMR bits */
-	edma_write_array(ecc, EDMA_EMCR, j, mask);
-	/* Clear any SER */
-	edma_shadow0_write_array(ecc, SH_SECR, j, mask);
-	edma_write(ecc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
-}
-
-/* Move channel to a specific event queue */
-static void edma_assign_channel_eventq(struct edma_chan *echan,
-				       enum dma_event_q eventq_no)
-{
-	struct edma_cc *ecc = echan->ecc;
-	int channel = EDMA_CHAN_SLOT(echan->ch_num);
-	int bit = (channel & 0x7) * 4;
-
-	/* default to low priority queue */
-	if (eventq_no == EVENTQ_DEFAULT)
-		eventq_no = ecc->default_queue;
-	if (eventq_no >= ecc->num_tc)
-		return;
-
-	eventq_no &= 7;
-	edma_modify_array(ecc, EDMA_DMAQNUM, (channel >> 3), ~(0x7 << bit),
-			  eventq_no << bit);
-}
-
-static int edma_alloc_channel(struct edma_chan *echan,
-			      enum dma_event_q eventq_no)
-{
-	struct edma_cc *ecc = echan->ecc;
-	int channel = EDMA_CHAN_SLOT(echan->ch_num);
-
-	/* ensure access through shadow region 0 */
-	edma_or_array2(ecc, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
-
-	/* ensure no events are pending */
-	edma_stop(echan);
-
-	edma_setup_interrupt(echan, true);
-
-	edma_assign_channel_eventq(echan, eventq_no);
-
-	return 0;
-}
-
-static void edma_free_channel(struct edma_chan *echan)
-{
-	/* ensure no events are pending */
-	edma_stop(echan);
-	/* REVISIT should probably take out of shadow region 0 */
-	edma_setup_interrupt(echan, false);
-}
-
-static inline struct edma_cc *to_edma_cc(struct dma_device *d)
-{
-	return container_of(d, struct edma_cc, dma_slave);
-}
-
-static inline struct edma_chan *to_edma_chan(struct dma_chan *c)
-{
-	return container_of(c, struct edma_chan, vchan.chan);
-}
-
-static inline struct edma_desc *to_edma_desc(struct dma_async_tx_descriptor *tx)
-{
-	return container_of(tx, struct edma_desc, vdesc.tx);
-}
-
-static void edma_desc_free(struct virt_dma_desc *vdesc)
-{
-	kfree(container_of(vdesc, struct edma_desc, vdesc));
-}
-
-/* Dispatch a queued descriptor to the controller (caller holds lock) */
-static void edma_execute(struct edma_chan *echan)
-{
-	struct edma_cc *ecc = echan->ecc;
-	struct virt_dma_desc *vdesc;
-	struct edma_desc *edesc;
-	struct device *dev = echan->vchan.chan.device->dev;
-	int i, j, left, nslots;
-
-	if (!echan->edesc) {
-		/* Setup is needed for the first transfer */
-		vdesc = vchan_next_desc(&echan->vchan);
-		if (!vdesc)
-			return;
-		list_del(&vdesc->node);
-		echan->edesc = to_edma_desc(&vdesc->tx);
-	}
-
-	edesc = echan->edesc;
-
-	/* Find out how many left */
-	left = edesc->pset_nr - edesc->processed;
-	nslots = min(MAX_NR_SG, left);
-	edesc->sg_len = 0;
-
-	/* Write descriptor PaRAM set(s) */
-	for (i = 0; i < nslots; i++) {
-		j = i + edesc->processed;
-		edma_write_slot(ecc, echan->slot[i], &edesc->pset[j].param);
-		edesc->sg_len += edesc->pset[j].len;
-		dev_vdbg(dev,
-			 "\n pset[%d]:\n"
-			 "  chnum\t%d\n"
-			 "  slot\t%d\n"
-			 "  opt\t%08x\n"
-			 "  src\t%08x\n"
-			 "  dst\t%08x\n"
-			 "  abcnt\t%08x\n"
-			 "  ccnt\t%08x\n"
-			 "  bidx\t%08x\n"
-			 "  cidx\t%08x\n"
-			 "  lkrld\t%08x\n",
-			 j, echan->ch_num, echan->slot[i],
-			 edesc->pset[j].param.opt,
-			 edesc->pset[j].param.src,
-			 edesc->pset[j].param.dst,
-			 edesc->pset[j].param.a_b_cnt,
-			 edesc->pset[j].param.ccnt,
-			 edesc->pset[j].param.src_dst_bidx,
-			 edesc->pset[j].param.src_dst_cidx,
-			 edesc->pset[j].param.link_bcntrld);
-		/* Link to the previous slot if not the last set */
-		if (i != (nslots - 1))
-			edma_link(ecc, echan->slot[i], echan->slot[i + 1]);
-	}
-
-	edesc->processed += nslots;
-
-	/*
-	 * If this is either the last set in a set of SG-list transactions
-	 * then setup a link to the dummy slot, this results in all future
-	 * events being absorbed and that's OK because we're done
-	 */
-	if (edesc->processed == edesc->pset_nr) {
-		if (edesc->cyclic)
-			edma_link(ecc, echan->slot[nslots - 1], echan->slot[1]);
-		else
-			edma_link(ecc, echan->slot[nslots - 1],
-				  echan->ecc->dummy_slot);
-	}
-
-	if (echan->missed) {
-		/*
-		 * This happens due to setup times between intermediate
-		 * transfers in long SG lists which have to be broken up into
-		 * transfers of MAX_NR_SG
-		 */
-		dev_dbg(dev, "missed event on channel %d\n", echan->ch_num);
-		edma_clean_channel(echan);
-		edma_stop(echan);
-		edma_start(echan);
-		edma_trigger_channel(echan);
-		echan->missed = 0;
-	} else if (edesc->processed <= MAX_NR_SG) {
-		dev_dbg(dev, "first transfer starting on channel %d\n",
-			echan->ch_num);
-		edma_start(echan);
-	} else {
-		dev_dbg(dev, "chan: %d: completed %d elements, resuming\n",
-			echan->ch_num, edesc->processed);
-		edma_resume(echan);
-	}
-}
-
-static int edma_terminate_all(struct dma_chan *chan)
-{
-	struct edma_chan *echan = to_edma_chan(chan);
-	unsigned long flags;
-	LIST_HEAD(head);
-
-	spin_lock_irqsave(&echan->vchan.lock, flags);
-
-	/*
-	 * Stop DMA activity: we assume the callback will not be called
-	 * after edma_dma() returns (even if it does, it will see
-	 * echan->edesc is NULL and exit.)
-	 */
-	if (echan->edesc) {
-		edma_stop(echan);
-		/* Move the cyclic channel back to default queue */
-		if (!echan->tc && echan->edesc->cyclic)
-			edma_assign_channel_eventq(echan, EVENTQ_DEFAULT);
-
-		vchan_terminate_vdesc(&echan->edesc->vdesc);
-		echan->edesc = NULL;
-	}
-
-	vchan_get_all_descriptors(&echan->vchan, &head);
-	spin_unlock_irqrestore(&echan->vchan.lock, flags);
-	vchan_dma_desc_free_list(&echan->vchan, &head);
-
-	return 0;
-}
-
-static void edma_synchronize(struct dma_chan *chan)
-{
-	struct edma_chan *echan = to_edma_chan(chan);
-
-	vchan_synchronize(&echan->vchan);
-}
-
-static int edma_slave_config(struct dma_chan *chan,
-	struct dma_slave_config *cfg)
-{
-	struct edma_chan *echan = to_edma_chan(chan);
-
-	if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
-	    cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
-		return -EINVAL;
-
-	if (cfg->src_maxburst > chan->device->max_burst ||
-	    cfg->dst_maxburst > chan->device->max_burst)
-		return -EINVAL;
-
-	memcpy(&echan->cfg, cfg, sizeof(echan->cfg));
-
-	return 0;
-}
-
-static int edma_dma_pause(struct dma_chan *chan)
-{
-	struct edma_chan *echan = to_edma_chan(chan);
-
-	if (!echan->edesc)
-		return -EINVAL;
-
-	edma_pause(echan);
-	return 0;
-}
-
-static int edma_dma_resume(struct dma_chan *chan)
-{
-	struct edma_chan *echan = to_edma_chan(chan);
-
-	edma_resume(echan);
-	return 0;
-}
-
-/*
- * A PaRAM set configuration abstraction used by other modes
- * @chan: Channel who's PaRAM set we're configuring
- * @pset: PaRAM set to initialize and setup.
- * @src_addr: Source address of the DMA
- * @dst_addr: Destination address of the DMA
- * @burst: In units of dev_width, how much to send
- * @dev_width: How much is the dev_width
- * @dma_length: Total length of the DMA transfer
- * @direction: Direction of the transfer
- */
-static int edma_config_pset(struct dma_chan *chan, struct edma_pset *epset,
-			    dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst,
-			    unsigned int acnt, unsigned int dma_length,
-			    enum dma_transfer_direction direction)
-{
-	struct edma_chan *echan = to_edma_chan(chan);
-	struct device *dev = chan->device->dev;
-	struct edmacc_param *param = &epset->param;
-	int bcnt, ccnt, cidx;
-	int src_bidx, dst_bidx, src_cidx, dst_cidx;
-	int absync;
-
-	/* src/dst_maxburst == 0 is the same case as src/dst_maxburst == 1 */
-	if (!burst)
-		burst = 1;
-	/*
-	 * If the maxburst is equal to the fifo width, use
-	 * A-synced transfers. This allows for large contiguous
-	 * buffer transfers using only one PaRAM set.
-	 */
-	if (burst == 1) {
-		/*
-		 * For the A-sync case, bcnt and ccnt are the remainder
-		 * and quotient respectively of the division of:
-		 * (dma_length / acnt) by (SZ_64K -1). This is so
-		 * that in case bcnt over flows, we have ccnt to use.
-		 * Note: In A-sync tranfer only, bcntrld is used, but it
-		 * only applies for sg_dma_len(sg) >= SZ_64K.
-		 * In this case, the best way adopted is- bccnt for the
-		 * first frame will be the remainder below. Then for
-		 * every successive frame, bcnt will be SZ_64K-1. This
-		 * is assured as bcntrld = 0xffff in end of function.
-		 */
-		absync = false;
-		ccnt = dma_length / acnt / (SZ_64K - 1);
-		bcnt = dma_length / acnt - ccnt * (SZ_64K - 1);
-		/*
-		 * If bcnt is non-zero, we have a remainder and hence an
-		 * extra frame to transfer, so increment ccnt.
-		 */
-		if (bcnt)
-			ccnt++;
-		else
-			bcnt = SZ_64K - 1;
-		cidx = acnt;
-	} else {
-		/*
-		 * If maxburst is greater than the fifo address_width,
-		 * use AB-synced transfers where A count is the fifo
-		 * address_width and B count is the maxburst. In this
-		 * case, we are limited to transfers of C count frames
-		 * of (address_width * maxburst) where C count is limited
-		 * to SZ_64K-1. This places an upper bound on the length
-		 * of an SG segment that can be handled.
-		 */
-		absync = true;
-		bcnt = burst;
-		ccnt = dma_length / (acnt * bcnt);
-		if (ccnt > (SZ_64K - 1)) {
-			dev_err(dev, "Exceeded max SG segment size\n");
-			return -EINVAL;
-		}
-		cidx = acnt * bcnt;
-	}
-
-	epset->len = dma_length;
-
-	if (direction == DMA_MEM_TO_DEV) {
-		src_bidx = acnt;
-		src_cidx = cidx;
-		dst_bidx = 0;
-		dst_cidx = 0;
-		epset->addr = src_addr;
-	} else if (direction == DMA_DEV_TO_MEM)  {
-		src_bidx = 0;
-		src_cidx = 0;
-		dst_bidx = acnt;
-		dst_cidx = cidx;
-		epset->addr = dst_addr;
-	} else if (direction == DMA_MEM_TO_MEM)  {
-		src_bidx = acnt;
-		src_cidx = cidx;
-		dst_bidx = acnt;
-		dst_cidx = cidx;
-	} else {
-		dev_err(dev, "%s: direction not implemented yet\n", __func__);
-		return -EINVAL;
-	}
-
-	param->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
-	/* Configure A or AB synchronized transfers */
-	if (absync)
-		param->opt |= SYNCDIM;
-
-	param->src = src_addr;
-	param->dst = dst_addr;
-
-	param->src_dst_bidx = (dst_bidx << 16) | src_bidx;
-	param->src_dst_cidx = (dst_cidx << 16) | src_cidx;
-
-	param->a_b_cnt = bcnt << 16 | acnt;
-	param->ccnt = ccnt;
-	/*
-	 * Only time when (bcntrld) auto reload is required is for
-	 * A-sync case, and in this case, a requirement of reload value
-	 * of SZ_64K-1 only is assured. 'link' is initially set to NULL
-	 * and then later will be populated by edma_execute.
-	 */
-	param->link_bcntrld = 0xffffffff;
-	return absync;
-}
-
-static struct dma_async_tx_descriptor *edma_prep_slave_sg(
-	struct dma_chan *chan, struct scatterlist *sgl,
-	unsigned int sg_len, enum dma_transfer_direction direction,
-	unsigned long tx_flags, void *context)
-{
-	struct edma_chan *echan = to_edma_chan(chan);
-	struct device *dev = chan->device->dev;
-	struct edma_desc *edesc;
-	dma_addr_t src_addr = 0, dst_addr = 0;
-	enum dma_slave_buswidth dev_width;
-	u32 burst;
-	struct scatterlist *sg;
-	int i, nslots, ret;
-
-	if (unlikely(!echan || !sgl || !sg_len))
-		return NULL;
-
-	if (direction == DMA_DEV_TO_MEM) {
-		src_addr = echan->cfg.src_addr;
-		dev_width = echan->cfg.src_addr_width;
-		burst = echan->cfg.src_maxburst;
-	} else if (direction == DMA_MEM_TO_DEV) {
-		dst_addr = echan->cfg.dst_addr;
-		dev_width = echan->cfg.dst_addr_width;
-		burst = echan->cfg.dst_maxburst;
-	} else {
-		dev_err(dev, "%s: bad direction: %d\n", __func__, direction);
-		return NULL;
-	}
-
-	if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
-		dev_err(dev, "%s: Undefined slave buswidth\n", __func__);
-		return NULL;
-	}
-
-	edesc = kzalloc(sizeof(*edesc) + sg_len * sizeof(edesc->pset[0]),
-			GFP_ATOMIC);
-	if (!edesc)
-		return NULL;
-
-	edesc->pset_nr = sg_len;
-	edesc->residue = 0;
-	edesc->direction = direction;
-	edesc->echan = echan;
-
-	/* Allocate a PaRAM slot, if needed */
-	nslots = min_t(unsigned, MAX_NR_SG, sg_len);
-
-	for (i = 0; i < nslots; i++) {
-		if (echan->slot[i] < 0) {
-			echan->slot[i] =
-				edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY);
-			if (echan->slot[i] < 0) {
-				kfree(edesc);
-				dev_err(dev, "%s: Failed to allocate slot\n",
-					__func__);
-				return NULL;
-			}
-		}
-	}
-
-	/* Configure PaRAM sets for each SG */
-	for_each_sg(sgl, sg, sg_len, i) {
-		/* Get address for each SG */
-		if (direction == DMA_DEV_TO_MEM)
-			dst_addr = sg_dma_address(sg);
-		else
-			src_addr = sg_dma_address(sg);
-
-		ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
-				       dst_addr, burst, dev_width,
-				       sg_dma_len(sg), direction);
-		if (ret < 0) {
-			kfree(edesc);
-			return NULL;
-		}
-
-		edesc->absync = ret;
-		edesc->residue += sg_dma_len(sg);
-
-		if (i == sg_len - 1)
-			/* Enable completion interrupt */
-			edesc->pset[i].param.opt |= TCINTEN;
-		else if (!((i+1) % MAX_NR_SG))
-			/*
-			 * Enable early completion interrupt for the
-			 * intermediateset. In this case the driver will be
-			 * notified when the paRAM set is submitted to TC. This
-			 * will allow more time to set up the next set of slots.
-			 */
-			edesc->pset[i].param.opt |= (TCINTEN | TCCMODE);
-	}
-	edesc->residue_stat = edesc->residue;
-
-	return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
-}
-
-static struct dma_async_tx_descriptor *edma_prep_dma_memcpy(
-	struct dma_chan *chan, dma_addr_t des