diff options
| author | Peter De-Schrijver <pdeschrijver@nvidia.com> | 2018-07-12 14:53:02 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2018-07-25 14:26:22 -0700 |
| commit | c76a69e477b88f259bcc118129874011abcaae86 (patch) | |
| tree | 4b4afa912eb95044ea1c799ac4d10c455c0512b4 /drivers/clk/tegra/clk-tegra210.c | |
| parent | 633e79650b4f0ed8cd26076a376b5372c413b0f8 (diff) | |
clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks
These clocks have low jitter paths to certain parents. To model these
correctly, use the sdmmc mux divider clock type.
Signed-off-by: Peter De-Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Aapo Vienamo <avienamo@nvidia.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/tegra/clk-tegra210.c')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra210.c | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index 5435d01c636a..9eb1cb14fce1 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -44,6 +44,8 @@ #define CLK_SOURCE_EMC 0x19c #define CLK_SOURCE_SOR1 0x410 #define CLK_SOURCE_LA 0x1f8 +#define CLK_SOURCE_SDMMC2 0x154 +#define CLK_SOURCE_SDMMC4 0x164 #define PLLC_BASE 0x80 #define PLLC_OUT 0x84 @@ -2286,11 +2288,9 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = { [tegra_clk_rtc] = { .dt_id = TEGRA210_CLK_RTC, .present = true }, [tegra_clk_timer] = { .dt_id = TEGRA210_CLK_TIMER, .present = true }, [tegra_clk_uarta_8] = { .dt_id = TEGRA210_CLK_UARTA, .present = true }, - [tegra_clk_sdmmc2_9] = { .dt_id = TEGRA210_CLK_SDMMC2, .present = true }, [tegra_clk_i2s1] = { .dt_id = TEGRA210_CLK_I2S1, .present = true }, [tegra_clk_i2c1] = { .dt_id = TEGRA210_CLK_I2C1, .present = true }, [tegra_clk_sdmmc1_9] = { .dt_id = TEGRA210_CLK_SDMMC1, .present = true }, - [tegra_clk_sdmmc4_9] = { .dt_id = TEGRA210_CLK_SDMMC4, .present = true }, [tegra_clk_pwm] = { .dt_id = TEGRA210_CLK_PWM, .present = true }, [tegra_clk_i2s2] = { .dt_id = TEGRA210_CLK_I2S2, .present = true }, [tegra_clk_usbd] = { .dt_id = TEGRA210_CLK_USBD, .present = true }, @@ -3030,6 +3030,16 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base, 0, NULL); clks[TEGRA210_CLK_ACLK] = clk; + clk = tegra_clk_register_sdmmc_mux_div("sdmmc2", clk_base, + CLK_SOURCE_SDMMC2, 9, + TEGRA_DIVIDER_ROUND_UP, 0, NULL); + clks[TEGRA210_CLK_SDMMC2] = clk; + + clk = tegra_clk_register_sdmmc_mux_div("sdmmc4", clk_base, + CLK_SOURCE_SDMMC4, 15, + TEGRA_DIVIDER_ROUND_UP, 0, NULL); + clks[TEGRA210_CLK_SDMMC4] = clk; + for (i = 0; i < ARRAY_SIZE(tegra210_periph); i++) { struct tegra_periph_init_data *init = &tegra210_periph[i]; struct clk **clkp; |