diff options
| author | Dinh Nguyen <dinguyen@altera.com> | 2014-05-12 12:27:22 -0500 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@altera.com> | 2014-05-12 12:27:22 -0500 |
| commit | 0691bb1b5a1865b3bbc9b7ce6e26eff546abb1cf (patch) | |
| tree | 1011296d0c0a3ec703f73880c96667be0f569eee /drivers/clk/socfpga/clk-gate.c | |
| parent | d1db0eea852497762cab43b905b879dfcd3b8987 (diff) | |
clk: socfpga: add divider registers to the main pll outputs
The C0(mpu_clk), C1(main_clk), and C2(dbg_base_clk) outputs from the main
PLL go through a pre-divider before coming into the system. These registers
were hidden for the CycloneV platform, but are now used for the ArriaV
platform.
This patch updates the clock driver to read the div-reg property for the
socfpga-periph-clk clocks. Also moves the div_mask define to clk.h for re-use.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Diffstat (limited to 'drivers/clk/socfpga/clk-gate.c')
| -rw-r--r-- | drivers/clk/socfpga/clk-gate.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c index 501d513bf890..dd3a78c64795 100644 --- a/drivers/clk/socfpga/clk-gate.c +++ b/drivers/clk/socfpga/clk-gate.c @@ -32,7 +32,6 @@ #define SOCFPGA_MMC_CLK "sdmmc_clk" #define SOCFPGA_GPIO_DB_CLK_OFFSET 0xA8 -#define div_mask(width) ((1 << (width)) - 1) #define streq(a, b) (strcmp((a), (b)) == 0) #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw) |