diff options
| author | Icenowy Zheng <icenowy@aosc.io> | 2017-09-10 20:40:05 +0800 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2017-09-17 12:03:08 +0200 |
| commit | 62d212bdb022deeb875f92f6e376c799e3f35eca (patch) | |
| tree | 7ad60e3793d321145ba9c29de69f75523a42dba9 /drivers/accessibility | |
| parent | 2bd6bf03f4c1c59381d62c61d03f6cc3fe71f66e (diff) | |
clk: sunxi-ng: add CLK_SET_RATE_UNGATE to all H3 PLLs
The PLLs on H3 have a lock bit, which will only be set to 1 when the PLL
is really working.
Add CLK_SET_RATE_UNGATE to the PLLs, otherwise it will timeout when
trying to set PLL clock frequency without enabling it.
Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'drivers/accessibility')
0 files changed, 0 insertions, 0 deletions