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authorMike Travis <travis@sgi.com>2013-02-11 13:45:15 -0600
committerH. Peter Anvin <hpa@linux.intel.com>2013-02-11 17:18:25 -0800
commitd924f947a44684796eee6fa488a9fe7876923c3b (patch)
tree6c515eb97561b05dc9bb39cbd60b3b12e47d5575 /arch
parent385404e0ce4dbceb72f3f89cb172b2e60ef8e6d3 (diff)
x86, uv, uv3: Trim MMR register definitions after code changes for SGI UV3
This patch trims the MMR register definitions after the updates for the SGI UV3 system have been applied. Note that because these definitions are automatically generated from the RTL we cannot control the length of the names. Therefore there are lines that exceed 80 characters. Signed-off-by: Mike Travis <travis@sgi.com> Link: http://lkml.kernel.org/r/20130211194509.173026880@gulag1.americas.sgi.com Acked-by: Russ Anderson <rja@sgi.com> Reviewed-by: Dimitri Sivanich <sivanich@sgi.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/x86/include/asm/uv/uv_mmrs.h2480
1 files changed, 1 insertions, 2479 deletions
diff --git a/arch/x86/include/asm/uv/uv_mmrs.h b/arch/x86/include/asm/uv/uv_mmrs.h
index e1fa870ce782..bd5f80e58a23 100644
--- a/arch/x86/include/asm/uv/uv_mmrs.h
+++ b/arch/x86/include/asm/uv/uv_mmrs.h
@@ -73,7 +73,7 @@
* } sn;
* };
*
- * (GEN Flags: mflags_opt=c undefs=0 UV23=UVXH)
+ * (GEN Flags: mflags_opt= undefs=0 UV23=UVXH)
*/
#define UV_MMR_ENABLE (1UL << 63)
@@ -92,64 +92,24 @@
/* UVH_BAU_DATA_BROADCAST */
/* ========================================================================= */
#define UVH_BAU_DATA_BROADCAST 0x61688UL
-#define UV1H_BAU_DATA_BROADCAST 0x61688UL
-#define UV2H_BAU_DATA_BROADCAST 0x61688UL
-#define UV3H_BAU_DATA_BROADCAST 0x61688UL
#define UVH_BAU_DATA_BROADCAST_32 0x440
-#define UV1H_BAU_DATA_BROADCAST_32 0x61688UL
-#define UV2H_BAU_DATA_BROADCAST_32 0x61688UL
-#define UV3H_BAU_DATA_BROADCAST_32 0x61688UL
#define UVH_BAU_DATA_BROADCAST_ENABLE_SHFT 0
#define UVH_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL
-#define UV1H_BAU_DATA_BROADCAST_ENABLE_SHFT 0
-#define UV1H_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL
-
-#define UVXH_BAU_DATA_BROADCAST_ENABLE_SHFT 0
-#define UVXH_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL
-
-#define UV2H_BAU_DATA_BROADCAST_ENABLE_SHFT 0
-#define UV2H_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL
-
-#define UV3H_BAU_DATA_BROADCAST_ENABLE_SHFT 0
-#define UV3H_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL
-
union uvh_bau_data_broadcast_u {
unsigned long v;
struct uvh_bau_data_broadcast_s {
unsigned long enable:1; /* RW */
unsigned long rsvd_1_63:63;
} s;
- struct uv1h_bau_data_broadcast_s {
- unsigned long enable:1; /* RW */
- unsigned long rsvd_1_63:63;
- } s1;
- struct uvxh_bau_data_broadcast_s {
- unsigned long enable:1; /* RW */
- unsigned long rsvd_1_63:63;
- } sx;
- struct uv2h_bau_data_broadcast_s {
- unsigned long enable:1; /* RW */
- unsigned long rsvd_1_63:63;
- } s2;
- struct uv3h_bau_data_broadcast_s {
- unsigned long enable:1; /* RW */
- unsigned long rsvd_1_63:63;
- } s3;
};
/* ========================================================================= */
/* UVH_BAU_DATA_CONFIG */
/* ========================================================================= */
#define UVH_BAU_DATA_CONFIG 0x61680UL
-#define UV1H_BAU_DATA_CONFIG 0x61680UL
-#define UV2H_BAU_DATA_CONFIG 0x61680UL
-#define UV3H_BAU_DATA_CONFIG 0x61680UL
#define UVH_BAU_DATA_CONFIG_32 0x438
-#define UV1H_BAU_DATA_CONFIG_32 0x61680UL
-#define UV2H_BAU_DATA_CONFIG_32 0x61680UL
-#define UV3H_BAU_DATA_CONFIG_32 0x61680UL
#define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0
#define UVH_BAU_DATA_CONFIG_DM_SHFT 8
@@ -168,74 +128,6 @@ union uvh_bau_data_broadcast_u {
#define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL
#define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
-#define UV1H_BAU_DATA_CONFIG_VECTOR_SHFT 0
-#define UV1H_BAU_DATA_CONFIG_DM_SHFT 8
-#define UV1H_BAU_DATA_CONFIG_DESTMODE_SHFT 11
-#define UV1H_BAU_DATA_CONFIG_STATUS_SHFT 12
-#define UV1H_BAU_DATA_CONFIG_P_SHFT 13
-#define UV1H_BAU_DATA_CONFIG_T_SHFT 15
-#define UV1H_BAU_DATA_CONFIG_M_SHFT 16
-#define UV1H_BAU_DATA_CONFIG_APIC_ID_SHFT 32
-#define UV1H_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL
-#define UV1H_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL
-#define UV1H_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL
-#define UV1H_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL
-#define UV1H_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL
-#define UV1H_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL
-#define UV1H_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL
-#define UV1H_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
-
-#define UVXH_BAU_DATA_CONFIG_VECTOR_SHFT 0
-#define UVXH_BAU_DATA_CONFIG_DM_SHFT 8
-#define UVXH_BAU_DATA_CONFIG_DESTMODE_SHFT 11
-#define UVXH_BAU_DATA_CONFIG_STATUS_SHFT 12
-#define UVXH_BAU_DATA_CONFIG_P_SHFT 13
-#define UVXH_BAU_DATA_CONFIG_T_SHFT 15
-#define UVXH_BAU_DATA_CONFIG_M_SHFT 16
-#define UVXH_BAU_DATA_CONFIG_APIC_ID_SHFT 32
-#define UVXH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL
-#define UVXH_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL
-#define UVXH_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL
-#define UVXH_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL
-#define UVXH_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL
-#define UVXH_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL
-#define UVXH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL
-#define UVXH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
-
-#define UV2H_BAU_DATA_CONFIG_VECTOR_SHFT 0
-#define UV2H_BAU_DATA_CONFIG_DM_SHFT 8
-#define UV2H_BAU_DATA_CONFIG_DESTMODE_SHFT 11
-#define UV2H_BAU_DATA_CONFIG_STATUS_SHFT 12
-#define UV2H_BAU_DATA_CONFIG_P_SHFT 13
-#define UV2H_BAU_DATA_CONFIG_T_SHFT 15
-#define UV2H_BAU_DATA_CONFIG_M_SHFT 16
-#define UV2H_BAU_DATA_CONFIG_APIC_ID_SHFT 32
-#define UV2H_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL
-#define UV2H_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL
-#define UV2H_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL
-#define UV2H_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL
-#define UV2H_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL
-#define UV2H_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL
-#define UV2H_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL
-#define UV2H_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
-
-#define UV3H_BAU_DATA_CONFIG_VECTOR_SHFT 0
-#define UV3H_BAU_DATA_CONFIG_DM_SHFT 8
-#define UV3H_BAU_DATA_CONFIG_DESTMODE_SHFT 11
-#define UV3H_BAU_DATA_CONFIG_STATUS_SHFT 12
-#define UV3H_BAU_DATA_CONFIG_P_SHFT 13
-#define UV3H_BAU_DATA_CONFIG_T_SHFT 15
-#define UV3H_BAU_DATA_CONFIG_M_SHFT 16
-#define UV3H_BAU_DATA_CONFIG_APIC_ID_SHFT 32
-#define UV3H_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL
-#define UV3H_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL
-#define UV3H_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL
-#define UV3H_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL
-#define UV3H_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL
-#define UV3H_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL
-#define UV3H_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL
-#define UV3H_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
-
union uvh_bau_data_config_u {
unsigned long v;
struct uvh_bau_data_config_s {
@@ -250,74 +142,19 @@ union uvh_bau_data_config_u {
unsigned long rsvd_17_31:15;
unsigned long apic_id:32; /* RW */
} s;
- struct uv1h_bau_data_config_s {
- unsigned long vector_:8; /* RW */
- unsigned long dm:3; /* RW */
- unsigned long destmode:1; /* RW */
- unsigned long status:1; /* RO */
- unsigned long p:1; /* RO */
- unsigned long rsvd_14:1;
- unsigned long t:1; /* RO */
- unsigned long m:1; /* RW */
- unsigned long rsvd_17_31:15;
- unsigned long apic_id:32; /* RW */
- } s1;
- struct uvxh_bau_data_config_s {
- unsigned long vector_:8; /* RW */
- unsigned long dm:3; /* RW */
- unsigned long destmode:1; /* RW */
- unsigned long status:1; /* RO */
- unsigned long p:1; /* RO */
- unsigned long rsvd_14:1;
- unsigned long t:1; /* RO */
- unsigned long m:1; /* RW */
- unsigned long rsvd_17_31:15;
- unsigned long apic_id:32; /* RW */
- } sx;
- struct uv2h_bau_data_config_s {
- unsigned long vector_:8; /* RW */
- unsigned long dm:3; /* RW */
- unsigned long destmode:1; /* RW */
- unsigned long status:1; /* RO */
- unsigned long p:1; /* RO */
- unsigned long rsvd_14:1;
- unsigned long t:1; /* RO */
- unsigned long m:1; /* RW */
- unsigned long rsvd_17_31:15;
- unsigned long apic_id:32; /* RW */
- } s2;
- struct uv3h_bau_data_config_s {
- unsigned long vector_:8; /* RW */
- unsigned long dm:3; /* RW */
- unsigned long destmode:1; /* RW */
- unsigned long status:1; /* RO */
- unsigned long p:1; /* RO */
- unsigned long rsvd_14:1;
- unsigned long t:1; /* RO */
- unsigned long m:1; /* RW */
- unsigned long rsvd_17_31:15;
- unsigned long apic_id:32; /* RW */
- } s3;
};
/* ========================================================================= */
/* UVH_EVENT_OCCURRED0 */
/* ========================================================================= */
#define UVH_EVENT_OCCURRED0 0x70000UL
-#define UV1H_EVENT_OCCURRED0 0x70000UL
-#define UV2H_EVENT_OCCURRED0 0x70000UL
-#define UV3H_EVENT_OCCURRED0 0x70000UL
#define UVH_EVENT_OCCURRED0_32 0x5e8
-#define UV1H_EVENT_OCCURRED0_32 0x70000UL
-#define UV2H_EVENT_OCCURRED0_32 0x70000UL
-#define UV3H_EVENT_OCCURRED0_32 0x70000UL
#define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT 0
#define UVH_EVENT_OCCURRED0_RH_AOERR0_SHFT 11
#define UVH_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
#define UVH_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
-#define UV1H_EVENT_OCCURRED0_LB_HCERR_SHFT 0
#define UV1H_EVENT_OCCURRED0_GR0_HCERR_SHFT 1
#define UV1H_EVENT_OCCURRED0_GR1_HCERR_SHFT 2
#define UV1H_EVENT_OCCURRED0_LH_HCERR_SHFT 3
@@ -328,7 +165,6 @@ union uvh_bau_data_config_u {
#define UV1H_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8
#define UV1H_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9
#define UV1H_EVENT_OCCURRED0_LH_AOERR0_SHFT 10
-#define UV1H_EVENT_OCCURRED0_RH_AOERR0_SHFT 11
#define UV1H_EVENT_OCCURRED0_XN_AOERR0_SHFT 12
#define UV1H_EVENT_OCCURRED0_SI_AOERR0_SHFT 13
#define UV1H_EVENT_OCCURRED0_LB_AOERR1_SHFT 14
@@ -374,7 +210,6 @@ union uvh_bau_data_config_u {
#define UV1H_EVENT_OCCURRED0_RTC3_SHFT 54
#define UV1H_EVENT_OCCURRED0_BAU_DATA_SHFT 55
#define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56
-#define UV1H_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
#define UV1H_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL
#define UV1H_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL
#define UV1H_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL
@@ -385,7 +220,6 @@ union uvh_bau_data_config_u {
#define UV1H_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL
#define UV1H_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL
#define UV1H_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL
-#define UV1H_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
#define UV1H_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL
#define UV1H_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL
#define UV1H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL
@@ -432,7 +266,6 @@ union uvh_bau_data_config_u {
#define UV1H_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL
#define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL
-#define UVXH_EVENT_OCCURRED0_LB_HCERR_SHFT 0
#define UVXH_EVENT_OCCURRED0_QP_HCERR_SHFT 1
#define UVXH_EVENT_OCCURRED0_RH_HCERR_SHFT 2
#define UVXH_EVENT_OCCURRED0_LH0_HCERR_SHFT 3
@@ -443,7 +276,6 @@ union uvh_bau_data_config_u {
#define UVXH_EVENT_OCCURRED0_NI1_HCERR_SHFT 8
#define UVXH_EVENT_OCCURRED0_LB_AOERR0_SHFT 9
#define UVXH_EVENT_OCCURRED0_QP_AOERR0_SHFT 10
-#define UVXH_EVENT_OCCURRED0_RH_AOERR0_SHFT 11
#define UVXH_EVENT_OCCURRED0_LH0_AOERR0_SHFT 12
#define UVXH_EVENT_OCCURRED0_LH1_AOERR0_SHFT 13
#define UVXH_EVENT_OCCURRED0_GR0_AOERR0_SHFT 14
@@ -491,7 +323,6 @@ union uvh_bau_data_config_u {
#define UVXH_EVENT_OCCURRED0_EXTIO_INT2_SHFT 56
#define UVXH_EVENT_OCCURRED0_EXTIO_INT3_SHFT 57
#define UVXH_EVENT_OCCURRED0_PROFILE_INT_SHFT 58
-#define UVXH_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
#define UVXH_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL
#define UVXH_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000004UL
#define UVXH_EVENT_OCCURRED0_LH0_HCERR_MASK 0x0000000000000008UL
@@ -502,7 +333,6 @@ union uvh_bau_data_config_u {
#define UVXH_EVENT_OCCURRED0_NI1_HCERR_MASK 0x0000000000000100UL
#define UVXH_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000200UL
#define UVXH_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL
-#define UVXH_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
#define UVXH_EVENT_OCCURRED0_LH0_AOERR0_MASK 0x0000000000001000UL
#define UVXH_EVENT_OCCURRED0_LH1_AOERR0_MASK 0x0000000000002000UL
#define UVXH_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000004000UL
@@ -551,244 +381,6 @@ union uvh_bau_data_config_u {
#define UVXH_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL
#define UVXH_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL
-#define UV2H_EVENT_OCCURRED0_LB_HCERR_SHFT 0
-#define UV2H_EVENT_OCCURRED0_QP_HCERR_SHFT 1
-#define UV2H_EVENT_OCCURRED0_RH_HCERR_SHFT 2
-#define UV2H_EVENT_OCCURRED0_LH0_HCERR_SHFT 3
-#define UV2H_EVENT_OCCURRED0_LH1_HCERR_SHFT 4
-#define UV2H_EVENT_OCCURRED0_GR0_HCERR_SHFT 5
-#define UV2H_EVENT_OCCURRED0_GR1_HCERR_SHFT 6
-#define UV2H_EVENT_OCCURRED0_NI0_HCERR_SHFT 7
-#define UV2H_EVENT_OCCURRED0_NI1_HCERR_SHFT 8
-#define UV2H_EVENT_OCCURRED0_LB_AOERR0_SHFT 9
-#define UV2H_EVENT_OCCURRED0_QP_AOERR0_SHFT 10
-#define UV2H_EVENT_OCCURRED0_RH_AOERR0_SHFT 11
-#define UV2H_EVENT_OCCURRED0_LH0_AOERR0_SHFT 12
-#define UV2H_EVENT_OCCURRED0_LH1_AOERR0_SHFT 13
-#define UV2H_EVENT_OCCURRED0_GR0_AOERR0_SHFT 14
-#define UV2H_EVENT_OCCURRED0_GR1_AOERR0_SHFT 15
-#define UV2H_EVENT_OCCURRED0_XB_AOERR0_SHFT 16
-#define UV2H_EVENT_OCCURRED0_RT_AOERR0_SHFT 17
-#define UV2H_EVENT_OCCURRED0_NI0_AOERR0_SHFT 18
-#define UV2H_EVENT_OCCURRED0_NI1_AOERR0_SHFT 19
-#define UV2H_EVENT_OCCURRED0_LB_AOERR1_SHFT 20
-#define UV2H_EVENT_OCCURRED0_QP_AOERR1_SHFT 21
-#define UV2H_EVENT_OCCURRED0_RH_AOERR1_SHFT 22
-#define UV2H_EVENT_OCCURRED0_LH0_AOERR1_SHFT 23
-#define UV2H_EVENT_OCCURRED0_LH1_AOERR1_SHFT 24
-#define UV2H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 25
-#define UV2H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 26
-#define UV2H_EVENT_OCCURRED0_XB_AOERR1_SHFT 27
-#define UV2H_EVENT_OCCURRED0_RT_AOERR1_SHFT 28
-#define UV2H_EVENT_OCCURRED0_NI0_AOERR1_SHFT 29
-#define UV2H_EVENT_OCCURRED0_NI1_AOERR1_SHFT 30
-#define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 31
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 32
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 33
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 34
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 35
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 36
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 37
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 38
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 39
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 40
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 41
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 42
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 43
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 44
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 45
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 46
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 47
-#define UV2H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 48
-#define UV2H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 49
-#define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 50
-#define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 51
-#define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 52
-#define UV2H_EVENT_OCCURRED0_IPI_INT_SHFT 53
-#define UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 54
-#define UV2H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 55
-#define UV2H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 56
-#define UV2H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 57
-#define UV2H_EVENT_OCCURRED0_PROFILE_INT_SHFT 58
-#define UV2H_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
-#define UV2H_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL
-#define UV2H_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000004UL
-#define UV2H_EVENT_OCCURRED0_LH0_HCERR_MASK 0x0000000000000008UL
-#define UV2H_EVENT_OCCURRED0_LH1_HCERR_MASK 0x0000000000000010UL
-#define UV2H_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000020UL
-#define UV2H_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000040UL
-#define UV2H_EVENT_OCCURRED0_NI0_HCERR_MASK 0x0000000000000080UL
-#define UV2H_EVENT_OCCURRED0_NI1_HCERR_MASK 0x0000000000000100UL
-#define UV2H_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000200UL
-#define UV2H_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL
-#define UV2H_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
-#define UV2H_EVENT_OCCURRED0_LH0_AOERR0_MASK 0x0000000000001000UL
-#define UV2H_EVENT_OCCURRED0_LH1_AOERR0_MASK 0x0000000000002000UL
-#define UV2H_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000004000UL
-#define UV2H_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000008000UL
-#define UV2H_EVENT_OCCURRED0_XB_AOERR0_MASK 0x0000000000010000UL
-#define UV2H_EVENT_OCCURRED0_RT_AOERR0_MASK 0x0000000000020000UL
-#define UV2H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000040000UL
-#define UV2H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000080000UL
-#define UV2H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000100000UL
-#define UV2H_EVENT_OCCURRED0_QP_AOERR1_MASK 0x0000000000200000UL
-#define UV2H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000400000UL
-#define UV2H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000000800000UL
-#define UV2H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000001000000UL
-#define UV2H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000002000000UL
-#define UV2H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000004000000UL
-#define UV2H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000008000000UL
-#define UV2H_EVENT_OCCURRED0_RT_AOERR1_MASK 0x0000000010000000UL
-#define UV2H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000020000000UL
-#define UV2H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000000040000000UL
-#define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000100000000UL
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000200000000UL
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000400000000UL
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000800000000UL
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000001000000000UL
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000002000000000UL
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000004000000000UL
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000008000000000UL
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000010000000000UL
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000020000000000UL
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000040000000000UL
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000080000000000UL
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000100000000000UL
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000200000000000UL
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000400000000000UL
-#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000800000000000UL
-#define UV2H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0001000000000000UL
-#define UV2H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0002000000000000UL
-#define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0004000000000000UL
-#define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0008000000000000UL
-#define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL
-#define UV2H_EVENT_OCCURRED0_IPI_INT_MASK 0x0020000000000000UL
-#define UV2H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0040000000000000UL
-#define UV2H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0080000000000000UL
-#define UV2H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0100000000000000UL
-#define UV2H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL
-#define UV2H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL
-
-#define UV3H_EVENT_OCCURRED0_LB_HCERR_SHFT 0
-#define UV3H_EVENT_OCCURRED0_QP_HCERR_SHFT 1
-#define UV3H_EVENT_OCCURRED0_RH_HCERR_SHFT 2
-#define UV3H_EVENT_OCCURRED0_LH0_HCERR_SHFT 3
-#define UV3H_EVENT_OCCURRED0_LH1_HCERR_SHFT 4
-#define UV3H_EVENT_OCCURRED0_GR0_HCERR_SHFT 5
-#define UV3H_EVENT_OCCURRED0_GR1_HCERR_SHFT 6
-#define UV3H_EVENT_OCCURRED0_NI0_HCERR_SHFT 7
-#define UV3H_EVENT_OCCURRED0_NI1_HCERR_SHFT 8
-#define UV3H_EVENT_OCCURRED0_LB_AOERR0_SHFT 9
-#define UV3H_EVENT_OCCURRED0_QP_AOERR0_SHFT 10
-#define UV3H_EVENT_OCCURRED0_RH_AOERR0_SHFT 11
-#define UV3H_EVENT_OCCURRED0_LH0_AOERR0_SHFT 12
-#define UV3H_EVENT_OCCURRED0_LH1_AOERR0_SHFT 13
-#define UV3H_EVENT_OCCURRED0_GR0_AOERR0_SHFT 14
-#define UV3H_EVENT_OCCURRED0_GR1_AOERR0_SHFT 15
-#define UV3H_EVENT_OCCURRED0_XB_AOERR0_SHFT 16
-#define UV3H_EVENT_OCCURRED0_RT_AOERR0_SHFT 17
-#define UV3H_EVENT_OCCURRED0_NI0_AOERR0_SHFT 18
-#define UV3H_EVENT_OCCURRED0_NI1_AOERR0_SHFT 19
-#define UV3H_EVENT_OCCURRED0_LB_AOERR1_SHFT 20
-#define UV3H_EVENT_OCCURRED0_QP_AOERR1_SHFT 21
-#define UV3H_EVENT_OCCURRED0_RH_AOERR1_SHFT 22
-#define UV3H_EVENT_OCCURRED0_LH0_AOERR1_SHFT 23
-#define UV3H_EVENT_OCCURRED0_LH1_AOERR1_SHFT 24
-#define UV3H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 25
-#define UV3H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 26
-#define UV3H_EVENT_OCCURRED0_XB_AOERR1_SHFT 27
-#define UV3H_EVENT_OCCURRED0_RT_AOERR1_SHFT 28
-#define UV3H_EVENT_OCCURRED0_NI0_AOERR1_SHFT 29
-#define UV3H_EVENT_OCCURRED0_NI1_AOERR1_SHFT 30
-#define UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 31
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 32
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 33
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 34
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 35
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 36
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 37
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 38
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 39
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 40
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 41
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 42
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 43
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 44
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 45
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 46
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 47
-#define UV3H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 48
-#define UV3H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 49
-#define UV3H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 50
-#define UV3H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 51
-#define UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 52
-#define UV3H_EVENT_OCCURRED0_IPI_INT_SHFT 53
-#define UV3H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 54
-#define UV3H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 55
-#define UV3H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 56
-#define UV3H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 57
-#define UV3H_EVENT_OCCURRED0_PROFILE_INT_SHFT 58
-#define UV3H_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
-#define UV3H_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL
-#define UV3H_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000004UL
-#define UV3H_EVENT_OCCURRED0_LH0_HCERR_MASK 0x0000000000000008UL
-#define UV3H_EVENT_OCCURRED0_LH1_HCERR_MASK 0x0000000000000010UL
-#define UV3H_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000020UL
-#define UV3H_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000040UL
-#define UV3H_EVENT_OCCURRED0_NI0_HCERR_MASK 0x0000000000000080UL
-#define UV3H_EVENT_OCCURRED0_NI1_HCERR_MASK 0x0000000000000100UL
-#define UV3H_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000200UL
-#define UV3H_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL
-#define UV3H_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
-#define UV3H_EVENT_OCCURRED0_LH0_AOERR0_MASK 0x0000000000001000UL
-#define UV3H_EVENT_OCCURRED0_LH1_AOERR0_MASK 0x0000000000002000UL
-#define UV3H_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000004000UL
-#define UV3H_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000008000UL
-#define UV3H_EVENT_OCCURRED0_XB_AOERR0_MASK 0x0000000000010000UL
-#define UV3H_EVENT_OCCURRED0_RT_AOERR0_MASK 0x0000000000020000UL
-#define UV3H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000040000UL
-#define UV3H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000080000UL
-#define UV3H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000100000UL
-#define UV3H_EVENT_OCCURRED0_QP_AOERR1_MASK 0x0000000000200000UL
-#define UV3H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000400000UL
-#define UV3H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000000800000UL
-#define UV3H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000001000000UL
-#define UV3H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000002000000UL
-#define UV3H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000004000000UL
-#define UV3H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000008000000UL
-#define UV3H_EVENT_OCCURRED0_RT_AOERR1_MASK 0x0000000010000000UL
-#define UV3H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000020000000UL
-#define UV3H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000000040000000UL
-#define UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000100000000UL
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000200000000UL
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000400000000UL
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000800000000UL
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000001000000000UL
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000002000000000UL
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000004000000000UL
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000008000000000UL
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000010000000000UL
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000020000000000UL
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000040000000000UL
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000080000000000UL
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000100000000000UL
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000200000000000UL
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000400000000000UL
-#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000800000000000UL
-#define UV3H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0001000000000000UL
-#define UV3H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0002000000000000UL
-#define UV3H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0004000000000000UL
-#define UV3H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0008000000000000UL
-#define UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL
-#define UV3H_EVENT_OCCURRED0_IPI_INT_MASK 0x0020000000000000UL
-#define UV3H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0040000000000000UL
-#define UV3H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0080000000000000UL
-#define UV3H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0100000000000000UL
-#define UV3H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL
-#define UV3H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL
-
union uvh_event_occurred0_u {
unsigned long v;
struct uvh_event_occurred0_s {
@@ -797,66 +389,6 @@ union uvh_event_occurred0_u {
unsigned long rh_aoerr0:1; /* RW, W1C */
unsigned long rsvd_12_63:52;
} s;
- struct uv1h_event_occurred0_s {
- unsigned long lb_hcerr:1; /* RW, W1C */
- unsigned long gr0_hcerr:1; /* RW, W1C */
- unsigned long gr1_hcerr:1; /* RW, W1C */
- unsigned long lh_hcerr:1; /* RW, W1C */
- unsigned long rh_hcerr:1; /* RW, W1C */
- unsigned long xn_hcerr:1; /* RW, W1C */
- unsigned long si_hcerr:1; /* RW, W1C */
- unsigned long lb_aoerr0:1; /* RW, W1C */
- unsigned long gr0_aoerr0:1; /* RW, W1C */
- unsigned long gr1_aoerr0:1; /* RW, W1C */
- unsigned long lh_aoerr0:1; /* RW, W1C */
- unsigned long rh_aoerr0:1; /* RW, W1C */
- unsigned long xn_aoerr0:1; /* RW, W1C */
- unsigned long si_aoerr0:1; /* RW, W1C */
- unsigned long lb_aoerr1:1; /* RW, W1C */
- unsigned long gr0_aoerr1:1; /* RW, W1C */
- unsigned long gr1_aoerr1:1; /* RW, W1C */
- unsigned long lh_aoerr1:1; /* RW, W1C */
- unsigned long rh_aoerr1:1; /* RW, W1C */
- unsigned long xn_aoerr1:1; /* RW, W1C */
- unsigned long si_aoerr1:1; /* RW, W1C */
- unsigned long rh_vpi_int:1; /* RW, W1C */
- unsigned long system_shutdown_int:1; /* RW, W1C */
- unsigned long lb_irq_int_0:1; /* RW, W1C */
- unsigned long lb_irq_int_1:1; /* RW, W1C */
- unsigned long lb_irq_int_2:1; /* RW, W1C */
- unsigned long lb_irq_int_3:1; /* RW, W1C */
- unsigned long lb_irq_int_4:1; /* RW, W1C */
- unsigned long lb_irq_int_5:1; /* RW, W1C */
- unsigned long lb_irq_int_6:1; /* RW, W1C */
- unsigned long lb_irq_int_7:1; /* RW, W1C */
- unsigned long lb_irq_int_8:1; /* RW, W1C */
- unsigned long lb_irq_int_9:1; /* RW, W1C */
- unsigned long lb_irq_int_10:1; /* RW, W1C */
- unsigned long lb_irq_int_11:1; /* RW, W1C */
- unsigned long lb_irq_int_12:1; /* RW, W1C */
- unsigned long lb_irq_int_13:1; /* RW, W1C */
- unsigned long lb_irq_int_14:1; /* RW, W1C */
- unsigned long lb_irq_int_15:1; /* RW, W1C */
- unsigned long l1_nmi_int:1; /* RW, W1C */
- unsigned long stop_clock:1; /* RW, W1C */
- unsigned long asic_to_l1:1; /* RW, W1C */
- unsigned long l1_to_asic:1; /* RW, W1C */
- unsigned long ltc_int:1; /* RW, W1C */
- unsigned long la_seq_trigger:1; /* RW, W1C */
- unsigned long ipi_int:1; /* RW, W1C */
- unsigned long extio_int0:1; /* RW, W1C */
- unsigned long extio_int1:1; /* RW, W1C */
- unsigned long extio_int2:1; /* RW, W1C */
- unsigned long extio_int3:1; /* RW, W1C */
- unsigned long profile_int:1; /* RW, W1C */
- unsigned long rtc0:1; /* RW, W1C */
- unsigned long rtc1:1; /* RW, W1C */
- unsigned long rtc2:1; /* RW, W1C */
- unsigned long rtc3:1; /* RW, W1C */
- unsigned long bau_data:1; /* RW, W1C */
- unsigned long power_management_req:1; /* RW, W1C */
- unsigned long rsvd_57_63:7;
- } s1;
struct uvxh_event_occurred0_s {
unsigned long lb_hcerr:1; /* RW */
unsigned long qp_hcerr:1; /* RW */
@@ -919,152 +451,19 @@ union uvh_event_occurred0_u {
unsigned long profile_int:1; /* RW */
unsigned long rsvd_59_63:5;
} sx;
- struct uv2h_event_occurred0_s {
- unsigned long lb_hcerr:1; /* RW */
- unsigned long qp_hcerr:1; /* RW */
- unsigned long rh_hcerr:1; /* RW */
- unsigned long lh0_hcerr:1; /* RW */
- unsigned long lh1_hcerr:1; /* RW */
- unsigned long gr0_hcerr:1; /* RW */
- unsigned long gr1_hcerr:1; /* RW */
- unsigned long ni0_hcerr:1; /* RW */
- unsigned long ni1_hcerr:1; /* RW */
- unsigned long lb_aoerr0:1; /* RW */
- unsigned long qp_aoerr0:1; /* RW */
- unsigned long rh_aoerr0:1; /* RW */
- unsigned long lh0_aoerr0:1; /* RW */
- unsigned long lh1_aoerr0:1; /* RW */
- unsigned long gr0_aoerr0:1; /* RW */
- unsigned long gr1_aoerr0:1; /* RW */
- unsigned long xb_aoerr0:1; /* RW */
- unsigned long rt_aoerr0:1; /* RW */
- unsigned long ni0_aoerr0:1; /* RW */
- unsigned long ni1_aoerr0:1; /* RW */
- unsigned long lb_aoerr1:1; /* RW */
- unsigned long qp_aoerr1:1; /* RW */
- unsigned long rh_aoerr1:1; /* RW */
- unsigned long lh0_aoerr1:1; /* RW */
- unsigned long lh1_aoerr1:1; /* RW */
- unsigned long gr0_aoerr1:1; /* RW */
- unsigned long gr1_aoerr1:1; /* RW */
- unsigned long xb_aoerr1:1; /* RW */
- unsigned long rt_aoerr1:1; /* RW */
- unsigned long ni0_aoerr1:1; /* RW */
- unsigned long ni1_aoerr1:1; /* RW */
- unsigned long system_shutdown_int:1; /* RW */
- unsigned long lb_irq_int_0:1; /* RW */
- unsigned long lb_irq_int_1:1; /* RW */
- unsigned long lb_irq_int_2:1; /* RW */
- unsigned long lb_irq_int_3:1; /* RW */
- unsigned long lb_irq_int_4:1; /* RW */
- unsigned long lb_irq_int_5:1; /* RW */
- unsigned long lb_irq_int_6:1; /* RW */
- unsigned long lb_irq_int_7:1; /* RW */
- unsigned long lb_irq_int_8:1; /* RW */
- unsigned long lb_irq_int_9:1; /* RW */
- unsigned long lb_irq_int_10:1; /* RW */
- unsigned long lb_irq_int_11:1; /* RW */
- unsigned long lb_irq_int_12:1; /* RW */
- unsigned long lb_irq_int_13:1; /* RW */
- unsigned long lb_irq_int_14:1; /* RW */
- unsigned long lb_irq_int_15:1; /* RW */
- unsigned long l1_nmi_int:1; /* RW */
- unsigned long stop_clock:1; /* RW */
- unsigned long asic_to_l1:1; /* RW */
- unsigned long l1_to_asic:1; /* RW */
- unsigned long la_seq_trigger:1; /* RW */
- unsigned long ipi_int:1; /* RW */
- unsigned long extio_int0:1; /* RW */
- unsigned long extio_int1:1; /* RW */
- unsigned long extio_int2:1; /* RW */
- unsigned long extio_int3:1; /* RW */
- unsigned long profile_int:1; /* RW */
- unsigned long rsvd_59_63:5;
- } s2;
- struct uv3h_event_occurred0_s {
- unsigned long lb_hcerr:1; /* RW */
- unsigned long qp_hcerr:1; /* RW */
- unsigned long rh_hcerr:1; /* RW */
- unsigned long lh0_hcerr:1; /* RW */
- unsigned long lh1_hcerr:1; /* RW */
- unsigned long gr0_hcerr:1; /* RW */
- unsigned long gr1_hcerr:1; /* RW */
- unsigned long ni0_hcerr:1; /* RW */
- unsigned long ni1_hcerr:1; /* RW */
- unsigned long lb_aoerr0:1; /* RW */
- unsigned long qp_aoerr0:1; /* RW */
- unsigned long rh_aoerr0:1; /* RW */
- unsigned long lh0_aoerr0:1; /* RW */
- unsigned long lh1_aoerr0:1; /* RW */
- unsigned long gr0_aoerr0:1; /* RW */
- unsigned long gr1_aoerr0:1; /* RW */
- unsigned long xb_aoerr0:1; /* RW */
- unsigned long rt_aoerr0:1; /* RW */
- unsigned long ni0_aoerr0:1; /* RW */
- unsigned long ni1_aoerr0:1; /* RW */
- unsigned long lb_aoerr1:1; /* RW */
- unsigned long qp_aoerr1:1; /* RW */
- unsigned long rh_aoerr1:1; /* RW */
- unsigned long lh0_aoerr1:1; /* RW */
- unsigned long lh1_aoerr1:1; /* RW */
- unsigned long gr0_aoerr1:1; /* RW */
- unsigned long gr1_aoerr1:1; /* RW */
- unsigned long xb_aoerr1:1; /* RW */
- unsigned long rt_aoerr1:1; /* RW */
- unsigned long ni0_aoerr1:1; /* RW */
- unsigned long ni1_aoerr1:1; /* RW */
- unsigned long system_shutdown_int:1; /* RW */
- unsigned long lb_irq_int_0:1; /* RW */
- unsigned long lb_irq_int_1:1; /* RW */
- unsigned long lb_irq_int_2:1; /* RW */
- unsigned long lb_irq_int_3:1; /* RW */
- unsigned long lb_irq_int_4:1; /* RW */
- unsigned long lb_irq_int_5:1; /* RW */
- unsigned long lb_irq_int_6:1; /* RW */
- unsigned long lb_irq_int_7:1; /* RW */
- unsigned long lb_irq_int_8:1; /* RW */
- unsigned long lb_irq_int_9:1; /* RW */
- unsigned long lb_irq_int_10:1; /* RW */
- unsigned long lb_irq_int_11:1; /* RW */
- unsigned long lb_irq_int_12:1; /* RW */
- unsigned long lb_irq_int_13:1; /* RW */
- unsigned long lb_irq_int_14:1; /* RW */
- unsigned long lb_irq_int_15:1; /* RW */
- unsigned long l1_nmi_int:1; /* RW */
- unsigned long stop_clock:1; /* RW */
- unsigned long asic_to_l1:1; /* RW */
- unsigned long l1_to_asic:1; /* RW */
- unsigned long la_seq_trigger:1; /* RW */
- unsigned long ipi_int:1; /* RW */
- unsigned long extio_int0:1; /* RW */
- unsigned long extio_int1:1; /* RW */
- unsigned long extio_int2:1; /* RW */
- unsigned long extio_int3:1; /* RW */
- unsigned long profile_int:1; /* RW */
- unsigned long rsvd_59_63:5;
- } s3;
};
/* ========================================================================= */
/* UVH_EVENT_OCCURRED0_ALIAS */
/* ========================================================================= */
#define UVH_EVENT_OCCURRED0_ALIAS 0x70008UL
-#define UV1H_EVENT_OCCURRED0_ALIAS 0x70008UL
-#define UV2H_EVENT_OCCURRED0_ALIAS 0x70008UL
-#define UV3H_EVENT_OCCURRED0_ALIAS 0x70008UL
#define UVH_EVENT_OCCURRED0_ALIAS_32 0x5f0
-#define UV1H_EVENT_OCCURRED0_ALIAS_32 0x70008UL
-#define UV2H_EVENT_OCCURRED0_ALIAS_32 0x70008UL
-#define UV3H_EVENT_OCCURRED0_ALIAS_32 0x70008UL
/* ========================================================================= */
/* UVH_GR0_TLB_INT0_CONFIG */
/* ========================================================================= */
#define UVH_GR0_TLB_INT0_CONFIG 0x61b00UL
-#define UV1H_GR0_TLB_INT0_CONFIG 0x61b00UL
-#define UV2H_GR0_TLB_INT0_CONFIG 0x61b00UL
-#define UV3H_GR0_TLB_INT0_CONFIG 0x61b00UL
#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0
#define UVH_GR0_TLB_INT0_CONFIG_DM_SHFT 8
@@ -1083,74 +482,6 @@ union uvh_event_occurred0_u {
#define UVH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
-#define UV1H_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0
-#define UV1H_GR0_TLB_INT0_CONFIG_DM_SHFT 8
-#define UV1H_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT 11
-#define UV1H_GR0_TLB_INT0_CONFIG_STATUS_SHFT 12
-#define UV1H_GR0_TLB_INT0_CONFIG_P_SHFT 13
-#define UV1H_GR0_TLB_INT0_CONFIG_T_SHFT 15
-#define UV1H_GR0_TLB_INT0_CONFIG_M_SHFT 16
-#define UV1H_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT 32
-#define UV1H_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
-#define UV1H_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
-#define UV1H_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
-#define UV1H_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
-#define UV1H_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
-#define UV1H_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
-#define UV1H_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
-#define UV1H_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
-
-#define UVXH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0
-#define UVXH_GR0_TLB_INT0_CONFIG_DM_SHFT 8
-#define UVXH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT 11
-#define UVXH_GR0_TLB_INT0_CONFIG_STATUS_SHFT 12
-#define UVXH_GR0_TLB_INT0_CONFIG_P_SHFT 13
-#define UVXH_GR0_TLB_INT0_CONFIG_T_SHFT 15
-#define UVXH_GR0_TLB_INT0_CONFIG_M_SHFT 16
-#define UVXH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT 32
-#define UVXH_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
-#define UVXH_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
-#define UVXH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
-#define UVXH_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
-#define UVXH_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
-#define UVXH_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
-#define UVXH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
-#define UVXH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
-
-#define UV2H_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0
-#define UV2H_GR0_TLB_INT0_CONFIG_DM_SHFT 8
-#define UV2H_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT 11
-#define UV2H_GR0_TLB_INT0_CONFIG_STATUS_SHFT 12
-#define UV2H_GR0_TLB_INT0_CONFIG_P_SHFT 13
-#define UV2H_GR0_TLB_INT0_CONFIG_T_SHFT 15
-#define UV2H_GR0_TLB_INT0_CONFIG_M_SHFT 16
-#define UV2H_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT 32
-#define UV2H_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
-#define UV2H_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
-#define UV2H_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
-#define UV2H_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
-#define UV2H_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
-#define UV2H_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
-#define UV2H_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
-#define UV2H_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
-
-#define UV3H_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0
-#define UV3H_GR0_TLB_INT0_CONFIG_DM_SHFT 8
-#define UV3H_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT 11
-#define UV3H_GR0_TLB_INT0_CONFIG_STATUS_SHFT 12
-#define UV3H_GR0_TLB_INT0_CONFIG_P_SHFT 13
-#define UV3H_GR0_TLB_INT0_CONFIG_T_SHFT 15
-#define UV3H_GR0_TLB_INT0_CONFIG_M_SHFT 16
-#define UV3H_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT 32
-#define UV3H_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
-#define UV3H_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
-#define UV3H_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
-#define UV3H_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
-#define UV3H_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
-#define UV3H_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
-#define UV3H_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
-#define UV3H_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
-
union uvh_gr0_tlb_int0_config_u {
unsigned long v;
struct uvh_gr0_tlb_int0_config_s {
@@ -1165,63 +496,12 @@ union uvh_gr0_tlb_int0_config_u {
unsigned long rsvd_17_31:15;
unsigned long apic_id:32; /* RW */
} s;
- struct uv1h_gr0_tlb_int0_config_s {
- unsigned long vector_:8; /* RW */
- unsigned long dm:3; /* RW */
- unsigned long destmode:1; /* RW */
- unsigned long sta