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authorPalmer Dabbelt <palmer@sifive.com>2017-12-01 13:10:42 -0800
committerPalmer Dabbelt <palmer@sifive.com>2017-12-01 13:10:42 -0800
commitf8182f613c9887744eb469b1a3352636481cb395 (patch)
treebb7872d1a46c98aa3fe9cd7c27f24bde1a4d1f90 /arch/riscv/include/asm/bitops.h
parent4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323 (diff)
parentbf730552734372e45b10fe056726de1950fdfdde (diff)
RISC-V Atomic Cleanups
This patch set is the result of some feedback that filtered through after our original patch set was reviewed, some of which was the result of me missing some email. It contains: * A new READ_ONCE in arch_spin_is_locked() * __test_and_op_bit_ord() is now actually ordered * Improvements to various comments * Removal of some dead code
Diffstat (limited to 'arch/riscv/include/asm/bitops.h')
-rw-r--r--arch/riscv/include/asm/bitops.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/include/asm/bitops.h b/arch/riscv/include/asm/bitops.h
index 7c281ef1d583..f30daf26f08f 100644
--- a/arch/riscv/include/asm/bitops.h
+++ b/arch/riscv/include/asm/bitops.h
@@ -67,7 +67,7 @@
: "memory");
#define __test_and_op_bit(op, mod, nr, addr) \
- __test_and_op_bit_ord(op, mod, nr, addr, )
+ __test_and_op_bit_ord(op, mod, nr, addr, .aqrl)
#define __op_bit(op, mod, nr, addr) \
__op_bit_ord(op, mod, nr, addr, )