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author | Linus Torvalds <torvalds@linux-foundation.org> | 2019-06-17 10:34:03 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2019-06-17 10:34:03 -0700 |
commit | eb7c825bf74755a9ea975b7a463c6d13ffa7f447 (patch) | |
tree | 80ab96bc7ca9a5711d3b6e53ce20b585c31d978b /arch/powerpc | |
parent | 9e0babf2c06c73cda2c0cd37a1653d823adb40ec (diff) | |
parent | 259931fd3b96e4386b361b7f80c1d89b266234c8 (diff) |
Merge tag 'riscv-for-v5.2/fixes-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V fixes from Paul Walmsley:
"This contains fixes, defconfig, and DT data changes for the v5.2-rc
series.
The fixes are relatively straightforward:
- Addition of a TLB fence in the vmalloc_fault path, so the CPU
doesn't enter an infinite page fault loop
- Readdition of the pm_power_off export, so device drivers that
reassign it can now be built as modules
- A udelay() fix for RV32, fixing a miscomputation of the delay time
- Removal of deprecated smp_mb__*() barriers
This also adds initial DT data infrastructure for arch/riscv, along
with initial data for the SiFive FU540-C000 SoC and the corresponding
HiFive Unleashed board.
We also update the RV64 defconfig to include some core drivers for the
FU540 in the build"
* tag 'riscv-for-v5.2/fixes-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
riscv: remove unused barrier defines
riscv: mm: synchronize MMU after pte change
riscv: dts: add initial board data for the SiFive HiFive Unleashed
riscv: dts: add initial support for the SiFive FU540-C000 SoC
dt-bindings: riscv: convert cpu binding to json-schema
dt-bindings: riscv: sifive: add YAML documentation for the SiFive FU540
arch: riscv: add support for building DTB files from DT source data
riscv: Fix udelay in RV32.
riscv: export pm_power_off again
RISC-V: defconfig: enable clocks, serial console
Diffstat (limited to 'arch/powerpc')
0 files changed, 0 insertions, 0 deletions