diff options
| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2017-09-06 15:20:55 +1000 |
|---|---|---|
| committer | Paul Mackerras <paulus@ozlabs.org> | 2017-09-12 16:02:07 +1000 |
| commit | d222af072380c4470295c07d84ecb15f4937e365 (patch) | |
| tree | 10fae9caad0faf7928465d2d7cffd892dfc5ce4d /arch/powerpc/kvm/book3s_hv_rm_xive.c | |
| parent | 5f54c8b2d4fad95d1f8ecbe023ebe6038e6d3760 (diff) | |
KVM: PPC: Book3S HV: Don't access XIVE PIPR register using byte accesses
The XIVE interrupt controller on POWER9 machines doesn't support byte
accesses to any register in the thread management area other than the
CPPR (current processor priority register). In particular, when
reading the PIPR (pending interrupt priority register), we need to
do a 32-bit or 64-bit load.
Cc: stable@vger.kernel.org # v4.13
Fixes: 2c4fb78f78b6 ("KVM: PPC: Book3S HV: Workaround POWER9 DD1.0 bug causing IPB bit loss")
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Diffstat (limited to 'arch/powerpc/kvm/book3s_hv_rm_xive.c')
| -rw-r--r-- | arch/powerpc/kvm/book3s_hv_rm_xive.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/powerpc/kvm/book3s_hv_rm_xive.c b/arch/powerpc/kvm/book3s_hv_rm_xive.c index abf5f01b6eb1..5b81a807d742 100644 --- a/arch/powerpc/kvm/book3s_hv_rm_xive.c +++ b/arch/powerpc/kvm/book3s_hv_rm_xive.c @@ -38,7 +38,6 @@ static inline void __iomem *get_tima_phys(void) #define __x_tima get_tima_phys() #define __x_eoi_page(xd) ((void __iomem *)((xd)->eoi_page)) #define __x_trig_page(xd) ((void __iomem *)((xd)->trig_page)) -#define __x_readb __raw_rm_readb #define __x_writeb __raw_rm_writeb #define __x_readw __raw_rm_readw #define __x_readq __raw_rm_readq |