diff options
| author | Nicholas Piggin <npiggin@gmail.com> | 2017-07-05 13:56:26 +1000 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2017-08-31 14:26:02 +1000 |
| commit | bded0706434dd34fe9d39a8f1bbb518154cacd7f (patch) | |
| tree | 6ee5925c92b291c104f242d9cc975d7b23713cf1 /arch/powerpc/kernel | |
| parent | a3b2cb30f252b21a6f962e0dd107c8b897ca65e4 (diff) | |
powerpc/pseries/le: Work around a firmware quirk
Some PowerVM firmware when delivering a system reset interrupt to a
little endian OS will mess up SRR registers. They are byteswapped, and
SRR1 is incorrect. An example from a crash:
NIP: 14dd0900000000c0
MSR: 1000000200000080
It's possible to detect this pattern in SRR1 (that would never happen
in normal operation), and at least fix the NIP. After this patch, the
same interrupt reports NIP properly:
NIP [c00000000009dd14] plpar_hcall_norets+0x1c/0x28
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/kernel')
0 files changed, 0 insertions, 0 deletions