ia64: remove support for the SGI SN2 platform

The SGI SN2 (early Altix) is a very non-standard IA64 platform that was
at the very high end of even IA64 hardware, and has been discontinued
a long time ago.  Remove it because there no upstream users left, and it
has magic hooks all over the kernel.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Link: https://lkml.kernel.org/r/20190813072514.23299-16-hch@lst.de
Signed-off-by: Tony Luck <tony.luck@intel.com>

40 files changed, 3 insertions, 10119 deletions

diff --git a/arch/ia64/include/asm/acpi.h b/arch/ia64/include/asm/acpi.h
index 0ea569040c5b..80c5ef8f475e 100644
--- a/arch/ia64/include/asm/acpi.h
+++ b/arch/ia64/include/asm/acpi.h
@@ -43,8 +43,6 @@ static inline const char *acpi_get_sysname (void)
 	return "hpzx1";
 # elif defined (CONFIG_IA64_HP_ZX1_SWIOTLB)
 	return "hpzx1_swiotlb";
-# elif defined (CONFIG_IA64_SGI_SN2)
-	return "sn2";
 # elif defined (CONFIG_IA64_SGI_UV)
 	return "uv";
 # elif defined (CONFIG_IA64_DIG)
diff --git a/arch/ia64/include/asm/irq.h b/arch/ia64/include/asm/irq.h
index 8b84a55ed38a..5acf52e90872 100644
--- a/arch/ia64/include/asm/irq.h
+++ b/arch/ia64/include/asm/irq.h
@@ -28,9 +28,6 @@ irq_canonicalize (int irq)
 }
 
 extern void set_irq_affinity_info (unsigned int irq, int dest, int redir);
-bool is_affinity_mask_valid(const struct cpumask *cpumask);
-
-#define is_affinity_mask_valid is_affinity_mask_valid
 
 int create_irq(void);
 void destroy_irq(unsigned int irq);
diff --git a/arch/ia64/include/asm/machvec.h b/arch/ia64/include/asm/machvec.h
index beae261fbcb4..d657f59d4fb3 100644
--- a/arch/ia64/include/asm/machvec.h
+++ b/arch/ia64/include/asm/machvec.h
@@ -101,8 +101,6 @@ extern void machvec_timer_interrupt (int, void *);
 #  include <asm/machvec_hpzx1.h>
 # elif defined (CONFIG_IA64_HP_ZX1_SWIOTLB)
 #  include <asm/machvec_hpzx1_swiotlb.h>
-# elif defined (CONFIG_IA64_SGI_SN2)
-#  include <asm/machvec_sn2.h>
 # elif defined (CONFIG_IA64_SGI_UV)
 #  include <asm/machvec_uv.h>
 # elif defined (CONFIG_IA64_GENERIC)
diff --git a/arch/ia64/include/asm/machvec_sn2.h b/arch/ia64/include/asm/machvec_sn2.h
deleted file mode 100644
index a243e4fb4877..000000000000
--- a/arch/ia64/include/asm/machvec_sn2.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright (c) 2002-2003,2006 Silicon Graphics, Inc.  All Rights Reserved.
- * 
- * This program is free software; you can redistribute it and/or modify it 
- * under the terms of version 2 of the GNU General Public License 
- * as published by the Free Software Foundation.
- * 
- * This program is distributed in the hope that it would be useful, but 
- * WITHOUT ANY WARRANTY; without even the implied warranty of 
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
- * 
- * Further, this software is distributed without any warranty that it is 
- * free of the rightful claim of any third person regarding infringement 
- * or the like.  Any license provided herein, whether implied or 
- * otherwise, applies only to this software file.  Patent licenses, if 
- * any, provided herein do not apply to combinations of this program with 
- * other software, or any other product whatsoever.
- * 
- * You should have received a copy of the GNU General Public 
- * License along with this program; if not, write the Free Software 
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- * 
- * For further information regarding this notice, see: 
- * 
- * http://oss.sgi.com/projects/GenInfo/NoticeExplan
- */
-
-#ifndef _ASM_IA64_MACHVEC_SN2_H
-#define _ASM_IA64_MACHVEC_SN2_H
-
-extern ia64_mv_setup_t sn_setup;
-extern ia64_mv_cpu_init_t sn_cpu_init;
-extern ia64_mv_irq_init_t sn_irq_init;
-extern ia64_mv_send_ipi_t sn2_send_IPI;
-extern ia64_mv_timer_interrupt_t sn_timer_interrupt;
-extern ia64_mv_global_tlb_purge_t sn2_global_tlb_purge;
-extern ia64_mv_irq_to_vector sn_irq_to_vector;
-extern ia64_mv_local_vector_to_irq sn_local_vector_to_irq;
-extern ia64_mv_pci_get_legacy_mem_t sn_pci_get_legacy_mem;
-extern ia64_mv_pci_legacy_read_t sn_pci_legacy_read;
-extern ia64_mv_pci_legacy_write_t sn_pci_legacy_write;
-extern ia64_mv_inb_t __sn_inb;
-extern ia64_mv_inw_t __sn_inw;
-extern ia64_mv_inl_t __sn_inl;
-extern ia64_mv_outb_t __sn_outb;
-extern ia64_mv_outw_t __sn_outw;
-extern ia64_mv_outl_t __sn_outl;
-extern ia64_mv_mmiowb_t __sn_mmiowb;
-extern ia64_mv_readb_t __sn_readb;
-extern ia64_mv_readw_t __sn_readw;
-extern ia64_mv_readl_t __sn_readl;
-extern ia64_mv_readq_t __sn_readq;
-extern ia64_mv_readb_t __sn_readb_relaxed;
-extern ia64_mv_readw_t __sn_readw_relaxed;
-extern ia64_mv_readl_t __sn_readl_relaxed;
-extern ia64_mv_readq_t __sn_readq_relaxed;
-extern ia64_mv_dma_init			sn_dma_init;
-extern ia64_mv_migrate_t		sn_migrate;
-extern ia64_mv_kernel_launch_event_t	sn_kernel_launch_event;
-extern ia64_mv_setup_msi_irq_t		sn_setup_msi_irq;
-extern ia64_mv_teardown_msi_irq_t	sn_teardown_msi_irq;
-extern ia64_mv_pci_fixup_bus_t		sn_pci_fixup_bus;
-
-
-/*
- * This stuff has dual use!
- *
- * For a generic kernel, the macros are used to initialize the
- * platform's machvec structure.  When compiling a non-generic kernel,
- * the macros are used directly.
- */
-#define ia64_platform_name		"sn2"
-#define platform_setup			sn_setup
-#define platform_cpu_init		sn_cpu_init
-#define platform_irq_init		sn_irq_init
-#define platform_send_ipi		sn2_send_IPI
-#define platform_timer_interrupt	sn_timer_interrupt
-#define platform_global_tlb_purge       sn2_global_tlb_purge
-#define platform_pci_fixup		sn_pci_fixup
-#define platform_inb			__sn_inb
-#define platform_inw			__sn_inw
-#define platform_inl			__sn_inl
-#define platform_outb			__sn_outb
-#define platform_outw			__sn_outw
-#define platform_outl			__sn_outl
-#define platform_mmiowb			__sn_mmiowb
-#define platform_readb			__sn_readb
-#define platform_readw			__sn_readw
-#define platform_readl			__sn_readl
-#define platform_readq			__sn_readq
-#define platform_readb_relaxed		__sn_readb_relaxed
-#define platform_readw_relaxed		__sn_readw_relaxed
-#define platform_readl_relaxed		__sn_readl_relaxed
-#define platform_readq_relaxed		__sn_readq_relaxed
-#define platform_irq_to_vector		sn_irq_to_vector
-#define platform_local_vector_to_irq	sn_local_vector_to_irq
-#define platform_pci_get_legacy_mem	sn_pci_get_legacy_mem
-#define platform_pci_legacy_read	sn_pci_legacy_read
-#define platform_pci_legacy_write	sn_pci_legacy_write
-#define platform_dma_init		sn_dma_init
-#define platform_migrate		sn_migrate
-#define platform_kernel_launch_event    sn_kernel_launch_event
-#ifdef CONFIG_PCI_MSI
-#define platform_setup_msi_irq		sn_setup_msi_irq
-#define platform_teardown_msi_irq	sn_teardown_msi_irq
-#else
-#define platform_setup_msi_irq		((ia64_mv_setup_msi_irq_t*)NULL)
-#define platform_teardown_msi_irq	((ia64_mv_teardown_msi_irq_t*)NULL)
-#endif
-#define platform_pci_fixup_bus		sn_pci_fixup_bus
-
-#include <asm/sn/io.h>
-
-#endif /* _ASM_IA64_MACHVEC_SN2_H */
diff --git a/arch/ia64/include/asm/mmzone.h b/arch/ia64/include/asm/mmzone.h
index e0de61709cf1..0ceca5f9449c 100644
--- a/arch/ia64/include/asm/mmzone.h
+++ b/arch/ia64/include/asm/mmzone.h
@@ -30,7 +30,7 @@ static inline int pfn_to_nid(unsigned long pfn)
 #ifdef CONFIG_IA64_DIG /* DIG systems are small */
 # define MAX_PHYSNODE_ID	8
 # define NR_NODE_MEMBLKS	(MAX_NUMNODES * 8)
-#else /* sn2 is the biggest case, so we use that if !DIG */
+#else
 # define MAX_PHYSNODE_ID	2048
 # define NR_NODE_MEMBLKS	(MAX_NUMNODES * 4)
 #endif
diff --git a/arch/ia64/include/asm/sn/acpi.h b/arch/ia64/include/asm/sn/acpi.h
deleted file mode 100644
index fd480db25565..000000000000
--- a/arch/ia64/include/asm/sn/acpi.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2006 Silicon Graphics, Inc. All rights reserved.
- */
-
-#ifndef _ASM_IA64_SN_ACPI_H
-#define _ASM_IA64_SN_ACPI_H
-
-extern int sn_acpi_rev;
-#define SN_ACPI_BASE_SUPPORT()   (sn_acpi_rev >= 0x20101)
-
-#endif /* _ASM_IA64_SN_ACPI_H */
diff --git a/arch/ia64/include/asm/sn/addrs.h b/arch/ia64/include/asm/sn/addrs.h
deleted file mode 100644
index e715c794b186..000000000000
--- a/arch/ia64/include/asm/sn/addrs.h
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (c) 1992-1999,2001-2005 Silicon Graphics, Inc. All rights reserved.
- */
-
-#ifndef _ASM_IA64_SN_ADDRS_H
-#define _ASM_IA64_SN_ADDRS_H
-
-#include <asm/percpu.h>
-#include <asm/sn/types.h>
-#include <asm/sn/arch.h>
-#include <asm/sn/pda.h>
-
-/*
- *  Memory/SHUB Address Format:
- *  +-+---------+--+--------------+
- *  |0|  NASID  |AS| NodeOffset   |
- *  +-+---------+--+--------------+
- *
- *  NASID: (low NASID bit is 0) Memory and SHUB MMRs
- *   AS: 2-bit Address Space Identifier. Used only if low NASID bit is 0
- *     00: Local Resources and MMR space
- *           Top bit of NodeOffset
- *               0: Local resources space
- *                  node id:
- *                        0: IA64/NT compatibility space
- *                        2: Local MMR Space
- *                        4: Local memory, regardless of local node id
- *               1: Global MMR space
- *     01: GET space.
- *     10: AMO space.
- *     11: Cacheable memory space.
- *
- *   NodeOffset: byte offset
- *
- *
- *  TIO address format:
- *  +-+----------+--+--------------+
- *  |0|  NASID   |AS| Nodeoffset   |
- *  +-+----------+--+--------------+
- *
- *  NASID: (low NASID bit is 1) TIO
- *   AS: 2-bit Chiplet Identifier
- *     00: TIO LB (Indicates TIO MMR access.)
- *     01: TIO ICE (indicates coretalk space access.)
- * 
- *   NodeOffset: top bit must be set.
- *
- *
- * Note that in both of the above address formats, the low
- * NASID bit indicates if the reference is to the SHUB or TIO MMRs.
- */
-
-
-/*
- * Define basic shift & mask constants for manipulating NASIDs and AS values.
- */
-#define NASID_BITMASK		(sn_hub_info->nasid_bitmask)
-#define NASID_SHIFT		(sn_hub_info->nasid_shift)
-#define AS_SHIFT		(sn_hub_info->as_shift)
-#define AS_BITMASK		0x3UL
-
-#define NASID_MASK              ((u64)NASID_BITMASK << NASID_SHIFT)
-#define AS_MASK			((u64)AS_BITMASK << AS_SHIFT)
-
-
-/*
- * AS values. These are the same on both SHUB1 & SHUB2.
- */
-#define AS_GET_VAL		1UL
-#define AS_AMO_VAL		2UL
-#define AS_CAC_VAL		3UL
-#define AS_GET_SPACE		(AS_GET_VAL << AS_SHIFT)
-#define AS_AMO_SPACE		(AS_AMO_VAL << AS_SHIFT)
-#define AS_CAC_SPACE		(AS_CAC_VAL << AS_SHIFT)
-
-
-/* 
- * Virtual Mode Local & Global MMR space.  
- */
-#define SH1_LOCAL_MMR_OFFSET	0x8000000000UL
-#define SH2_LOCAL_MMR_OFFSET	0x0200000000UL
-#define LOCAL_MMR_OFFSET	(is_shub2() ? SH2_LOCAL_MMR_OFFSET : SH1_LOCAL_MMR_OFFSET)
-#define LOCAL_MMR_SPACE		(__IA64_UNCACHED_OFFSET | LOCAL_MMR_OFFSET)
-#define LOCAL_PHYS_MMR_SPACE	(RGN_BASE(RGN_HPAGE) | LOCAL_MMR_OFFSET)
-
-#define SH1_GLOBAL_MMR_OFFSET	0x0800000000UL
-#define SH2_GLOBAL_MMR_OFFSET	0x0300000000UL
-#define GLOBAL_MMR_OFFSET	(is_shub2() ? SH2_GLOBAL_MMR_OFFSET : SH1_GLOBAL_MMR_OFFSET)
-#define GLOBAL_MMR_SPACE	(__IA64_UNCACHED_OFFSET | GLOBAL_MMR_OFFSET)
-
-/*
- * Physical mode addresses
- */
-#define GLOBAL_PHYS_MMR_SPACE	(RGN_BASE(RGN_HPAGE) | GLOBAL_MMR_OFFSET)
-
-
-/*
- * Clear region & AS bits.
- */
-#define TO_PHYS_MASK		(~(RGN_BITS | AS_MASK))
-
-
-/*
- * Misc NASID manipulation.
- */
-#define NASID_SPACE(n)		((u64)(n) << NASID_SHIFT)
-#define REMOTE_ADDR(n,a)	(NASID_SPACE(n) | (a))
-#define NODE_OFFSET(x)		((x) & (NODE_ADDRSPACE_SIZE - 1))
-#define NODE_ADDRSPACE_SIZE     (1UL << AS_SHIFT)
-#define NASID_GET(x)		(int) (((u64) (x) >> NASID_SHIFT) & NASID_BITMASK)
-#define LOCAL_MMR_ADDR(a)	(LOCAL_MMR_SPACE | (a))
-#define GLOBAL_MMR_ADDR(n,a)	(GLOBAL_MMR_SPACE | REMOTE_ADDR(n,a))
-#define GLOBAL_MMR_PHYS_ADDR(n,a) (GLOBAL_PHYS_MMR_SPACE | REMOTE_ADDR(n,a))
-#define GLOBAL_CAC_ADDR(n,a)	(CAC_BASE | REMOTE_ADDR(n,a))
-#define CHANGE_NASID(n,x)	((void *)(((u64)(x) & ~NASID_MASK) | NASID_SPACE(n)))
-#define IS_TIO_NASID(n)		((n) & 1)
-
-
-/* non-II mmr's start at top of big window space (4G) */
-#define BWIN_TOP		0x0000000100000000UL
-
-/*
- * general address defines
- */
-#define CAC_BASE		(PAGE_OFFSET | AS_CAC_SPACE)
-#define AMO_BASE		(__IA64_UNCACHED_OFFSET | AS_AMO_SPACE)
-#define AMO_PHYS_BASE		(RGN_BASE(RGN_HPAGE) | AS_AMO_SPACE)
-#define GET_BASE		(PAGE_OFFSET | AS_GET_SPACE)
-
-/*
- * Convert Memory addresses between various addressing modes.
- */
-#define TO_PHYS(x)		(TO_PHYS_MASK & (x))
-#define TO_CAC(x)		(CAC_BASE     | TO_PHYS(x))
-#ifdef CONFIG_SGI_SN
-#define TO_AMO(x)		(AMO_BASE     | TO_PHYS(x))
-#define TO_GET(x)		(GET_BASE     | TO_PHYS(x))
-#else
-#define TO_AMO(x)		({ BUG(); x; })
-#define TO_GET(x)		({ BUG(); x; })
-#endif
-
-/*
- * Covert from processor physical address to II/TIO physical address:
- *	II - squeeze out the AS bits
- *	TIO- requires a chiplet id in bits 38-39.  For DMA to memory,
- *           the chiplet id is zero.  If we implement TIO-TIO dma, we might need
- *           to insert a chiplet id into this macro.  However, it is our belief
- *           right now that this chiplet id will be ICE, which is also zero.
- */
-#define SH1_TIO_PHYS_TO_DMA(x) 						\
-	((((u64)(NASID_GET(x))) << 40) | NODE_OFFSET(x))
-
-#define SH2_NETWORK_BANK_OFFSET(x) 					\
-        ((u64)(x) & ((1UL << (sn_hub_info->nasid_shift - 4)) -1))
-
-#define SH2_NETWORK_BANK_SELECT(x) 					\
-        ((((u64)(x) & (0x3UL << (sn_hub_info->nasid_shift - 4)))	\
-        	>> (sn_hub_info->nasid_shift - 4)) << 36)
-
-#define SH2_NETWORK_ADDRESS(x) 						\
-	(SH2_NETWORK_BANK_OFFSET(x) | SH2_NETWORK_BANK_SELECT(x))
-
-#define SH2_TIO_PHYS_TO_DMA(x) 						\
-        (((u64)(NASID_GET(x)) << 40) | 	SH2_NETWORK_ADDRESS(x))
-
-#define PHYS_TO_TIODMA(x)						\
-	(is_shub1() ? SH1_TIO_PHYS_TO_DMA(x) : SH2_TIO_PHYS_TO_DMA(x))
-
-#define PHYS_TO_DMA(x)							\
-	((((u64)(x) & NASID_MASK) >> 2) | NODE_OFFSET(x))
-
-
-/*
- * Macros to test for address type.
- */
-#define IS_AMO_ADDRESS(x)	(((u64)(x) & (RGN_BITS | AS_MASK)) == AMO_BASE)
-#define IS_AMO_PHYS_ADDRESS(x)	(((u64)(x) & (RGN_BITS | AS_MASK)) == AMO_PHYS_BASE)
-
-
-/*
- * The following definitions pertain to the IO special address
- * space.  They define the location of the big and little windows
- * of any given node.
- */
-#define BWIN_SIZE_BITS			29	/* big window size: 512M */
-#define TIO_BWIN_SIZE_BITS		30	/* big window size: 1G */
-#define NODE_SWIN_BASE(n, w)		((w == 0) ? NODE_BWIN_BASE((n), SWIN0_BIGWIN) \
-		: RAW_NODE_SWIN_BASE(n, w))
-#define TIO_SWIN_BASE(n, w) 		(TIO_IO_BASE(n) + \
-					    ((u64) (w) << TIO_SWIN_SIZE_BITS))
-#define NODE_IO_BASE(n)			(GLOBAL_MMR_SPACE | NASID_SPACE(n))
-#define TIO_IO_BASE(n)                  (__IA64_UNCACHED_OFFSET | NASID_SPACE(n))
-#define BWIN_SIZE			(1UL << BWIN_SIZE_BITS)
-#define NODE_BWIN_BASE0(n)		(NODE_IO_BASE(n) + BWIN_SIZE)
-#define NODE_BWIN_BASE(n, w)		(NODE_BWIN_BASE0(n) + ((u64) (w) << BWIN_SIZE_BITS))
-#define RAW_NODE_SWIN_BASE(n, w)	(NODE_IO_BASE(n) + ((u64) (w) << SWIN_SIZE_BITS))
-#define BWIN_WIDGET_MASK		0x7
-#define BWIN_WINDOWNUM(x)		(((x) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
-#define SH1_IS_BIG_WINDOW_ADDR(x)	((x) & BWIN_TOP)
-
-#define TIO_BWIN_WINDOW_SELECT_MASK	0x7
-#define TIO_BWIN_WINDOWNUM(x)		(((x) >> TIO_BWIN_SIZE_BITS) & TIO_BWIN_WINDOW_SELECT_MASK)
-
-#define TIO_HWIN_SHIFT_BITS		33
-#define TIO_HWIN(x)			(NODE_OFFSET(x) >> TIO_HWIN_SHIFT_BITS)
-
-/*
- * The following definitions pertain to the IO special address
- * space.  They define the location of the big and little windows
- * of any given node.
- */
-
-#define SWIN_SIZE_BITS			24
-#define	SWIN_WIDGET_MASK		0xF
-
-#define TIO_SWIN_SIZE_BITS		28
-#define TIO_SWIN_SIZE			(1UL << TIO_SWIN_SIZE_BITS)
-#define TIO_SWIN_WIDGET_MASK		0x3
-
-/*
- * Convert smallwindow address to xtalk address.
- *
- * 'addr' can be physical or virtual address, but will be converted
- * to Xtalk address in the range 0 -> SWINZ_SIZEMASK
- */
-#define	SWIN_WIDGETNUM(x)		(((x)  >> SWIN_SIZE_BITS) & SWIN_WIDGET_MASK)
-#define TIO_SWIN_WIDGETNUM(x)		(((x)  >> TIO_SWIN_SIZE_BITS) & TIO_SWIN_WIDGET_MASK)
-
-
-/*
- * The following macros produce the correct base virtual address for
- * the hub registers. The REMOTE_HUB_* macro produce
- * the address for the specified hub's registers.  The intent is
- * that the appropriate PI, MD, NI, or II register would be substituted
- * for x.
- *
- *   WARNING:
- *	When certain Hub chip workaround are defined, it's not sufficient
- *	to dereference the *_HUB_ADDR() macros.  You should instead use
- *	HUB_L() and HUB_S() if you must deal with pointers to hub registers.
- *	Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S().
- *	They're always safe.
- */
-/* Shub1 TIO & MMR addressing macros */
-#define SH1_TIO_IOSPACE_ADDR(n,x)					\
-	GLOBAL_MMR_ADDR(n,x)
-
-#define SH1_REMOTE_BWIN_MMR(n,x)					\
-	GLOBAL_MMR_ADDR(n,x)
-
-#define SH1_REMOTE_SWIN_MMR(n,x)					\
-	(NODE_SWIN_BASE(n,1) + 0x800000UL + (x))
-
-#define SH1_REMOTE_MMR(n,x)						\
-	(SH1_IS_BIG_WINDOW_ADDR(x) ? SH1_REMOTE_BWIN_MMR(n,x) :		\
-	 	SH1_REMOTE_SWIN_MMR(n,x))
-
-/* Shub1 TIO & MMR addressing macros */
-#define SH2_TIO_IOSPACE_ADDR(n,x)					\
-	((__IA64_UNCACHED_OFFSET | REMOTE_ADDR(n,x) | 1UL << (NASID_SHIFT - 2)))
-
-#define SH2_REMOTE_MMR(n,x)						\
-	GLOBAL_MMR_ADDR(n,x)
-
-
-/* TIO & MMR addressing macros that work on both shub1 & shub2 */
-#define TIO_IOSPACE_ADDR(n,x)						\
-	((u64 *)(is_shub1() ? SH1_TIO_IOSPACE_ADDR(n,x) :		\
-		 SH2_TIO_IOSPACE_ADDR(n,x)))
-
-#define SH_REMOTE_MMR(n,x)						\
-	(is_shub1() ? SH1_REMOTE_MMR(n,x) : SH2_REMOTE_MMR(n,x))
-
-#define REMOTE_HUB_ADDR(n,x)						\
-	(IS_TIO_NASID(n) ?  ((volatile u64*)TIO_IOSPACE_ADDR(n,x)) :	\
-	 ((volatile u64*)SH_REMOTE_MMR(n,x)))
-
-
-#define HUB_L(x)			(*((volatile typeof(*x) *)x))
-#define	HUB_S(x,d)			(*((volatile typeof(*x) *)x) = (d))
-
-#define REMOTE_HUB_L(n, a)		HUB_L(REMOTE_HUB_ADDR((n), (a)))
-#define REMOTE_HUB_S(n, a, d)		HUB_S(REMOTE_HUB_ADDR((n), (a)), (d))
-
-/*
- * Coretalk address breakdown
- */
-#define CTALK_NASID_SHFT		40
-#define CTALK_NASID_MASK		(0x3FFFULL << CTALK_NASID_SHFT)
-#define CTALK_CID_SHFT			38
-#define CTALK_CID_MASK			(0x3ULL << CTALK_CID_SHFT)
-#define CTALK_NODE_OFFSET		0x3FFFFFFFFF
-
-#endif /* _ASM_IA64_SN_ADDRS_H */
diff --git a/arch/ia64/include/asm/sn/arch.h b/arch/ia64/include/asm/sn/arch.h
deleted file mode 100644
index 31eb784866f8..000000000000
--- a/arch/ia64/include/asm/sn/arch.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * SGI specific setup.
- *
- * Copyright (C) 1995-1997,1999,2001-2005 Silicon Graphics, Inc.  All rights reserved.
- * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
- */
-#ifndef _ASM_IA64_SN_ARCH_H
-#define _ASM_IA64_SN_ARCH_H
-
-#include <linux/numa.h>
-#include <asm/types.h>
-#include <asm/percpu.h>
-#include <asm/sn/types.h>
-#include <asm/sn/sn_cpuid.h>
-
-/*
- * This is the maximum number of NUMALINK nodes that can be part of a single
- * SSI kernel. This number includes C-brick, M-bricks, and TIOs. Nodes in
- * remote partitions are NOT included in this number.
- * The number of compact nodes cannot exceed size of a coherency domain.
- * The purpose of this define is to specify a node count that includes
- * all C/M/TIO nodes in an SSI system.
- *
- * SGI system can currently support up to 256 C/M nodes plus additional TIO nodes.
- *
- * 	Note: ACPI20 has an architectural limit of 256 nodes. When we upgrade
- * 	to ACPI3.0, this limit will be removed. The notion of "compact nodes"
- * 	should be deleted and TIOs should be included in MAX_NUMNODES.
- */
-#define MAX_TIO_NODES		MAX_NUMNODES
-#define MAX_COMPACT_NODES	(MAX_NUMNODES + MAX_TIO_NODES)
-
-/*
- * Maximum number of nodes in all partitions and in all coherency domains.
- * This is the total number of nodes accessible in the numalink fabric. It
- * includes all C & M bricks, plus all TIOs.
- *
- * This value is also the value of the maximum number of NASIDs in the numalink
- * fabric.
- */
-#define MAX_NUMALINK_NODES	16384
-
-/*
- * The following defines attributes of the HUB chip. These attributes are
- * frequently referenced. They are kept in the per-cpu data areas of each cpu.
- * They are kept together in a struct to minimize cache misses.
- */
-struct sn_hub_info_s {
-	u8 shub2;
-	u8 nasid_shift;
-	u8 as_shift;
-	u8 shub_1_1_found;
-	u16 nasid_bitmask;
-};
-DECLARE_PER_CPU(struct sn_hub_info_s, __sn_hub_info);
-#define sn_hub_info 	this_cpu_ptr(&__sn_hub_info)
-#define is_shub2()	(sn_hub_info->shub2)
-#define is_shub1()	(sn_hub_info->shub2 == 0)
-
-/*
- * Use this macro to test if shub 1.1 wars should be enabled
- */
-#define enable_shub_wars_1_1()	(sn_hub_info->shub_1_1_found)
-
-
-/*
- * Compact node ID to nasid mappings kept in the per-cpu data areas of each
- * cpu.
- */
-DECLARE_PER_CPU(short, __sn_cnodeid_to_nasid[MAX_COMPACT_NODES]);
-#define sn_cnodeid_to_nasid	this_cpu_ptr(&__sn_cnodeid_to_nasid[0])
-
-
-extern u8 sn_partition_id;
-extern u8 sn_system_size;
-extern u8 sn_sharing_domain_size;
-extern u8 sn_region_size;
-
-extern void sn_flush_all_caches(long addr, long bytes);
-extern bool sn_cpu_disable_allowed(int cpu);
-
-#endif /* _ASM_IA64_SN_ARCH_H */
diff --git a/arch/ia64/include/asm/sn/bte.h b/arch/ia64/include/asm/sn/bte.h
deleted file mode 100644
index cd71ab5faf62..000000000000
--- a/arch/ia64/include/asm/sn/bte.h
+++ /dev/null
@@ -1,236 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (c) 2000-2007 Silicon Graphics, Inc.  All Rights Reserved.
- */
-
-
-#ifndef _ASM_IA64_SN_BTE_H
-#define _ASM_IA64_SN_BTE_H
-
-#include <linux/timer.h>
-#include <linux/spinlock.h>
-#include <linux/cache.h>
-#include <asm/sn/pda.h>
-#include <asm/sn/types.h>
-#include <asm/sn/shub_mmr.h>
-
-struct nodepda_s;
-
-#define IBCT_NOTIFY             (0x1UL << 4)
-#define IBCT_ZFIL_MODE          (0x1UL << 0)
-
-/* #define BTE_DEBUG */
-/* #define BTE_DEBUG_VERBOSE */
-
-#ifdef BTE_DEBUG
-#  define BTE_PRINTK(x) printk x	/* Terse */
-#  ifdef BTE_DEBUG_VERBOSE
-#    define BTE_PRINTKV(x) printk x	/* Verbose */
-#  else
-#    define BTE_PRINTKV(x)
-#  endif /* BTE_DEBUG_VERBOSE */
-#else
-#  define BTE_PRINTK(x)
-#  define BTE_PRINTKV(x)
-#endif	/* BTE_DEBUG */
-
-
-/* BTE status register only supports 16 bits for length field */
-#define BTE_LEN_BITS (16)
-#define BTE_LEN_MASK ((1 << BTE_LEN_BITS) - 1)
-#define BTE_MAX_XFER (BTE_LEN_MASK << L1_CACHE_SHIFT)
-
-
-/* Define hardware */
-#define BTES_PER_NODE (is_shub2() ? 4 : 2)
-#define MAX_BTES_PER_NODE 4
-
-#define BTE2OFF_CTRL	0
-#define BTE2OFF_SRC	(SH2_BT_ENG_SRC_ADDR_0 - SH2_BT_ENG_CSR_0)
-#define BTE2OFF_DEST	(SH2_BT_ENG_DEST_ADDR_0 - SH2_BT_ENG_CSR_0)
-#define BTE2OFF_NOTIFY	(SH2_BT_ENG_NOTIF_ADDR_0 - SH2_BT_ENG_CSR_0)
-
-#define BTE_BASE_ADDR(interface) 				\
-    (is_shub2() ? (interface == 0) ? SH2_BT_ENG_CSR_0 :		\
-		  (interface == 1) ? SH2_BT_ENG_CSR_1 :		\
-		  (interface == 2) ? SH2_BT_ENG_CSR_2 :		\
-		  		     SH2_BT_ENG_CSR_3 		\
-		: (interface == 0) ? IIO_IBLS0 : IIO_IBLS1)
-
-#define BTE_SOURCE_ADDR(base)					\
-    (is_shub2() ? base + (BTE2OFF_SRC/8) 			\
-		: base + (BTEOFF_SRC/8))
-
-#define BTE_DEST_ADDR(base)					\
-    (is_shub2() ? base + (BTE2OFF_DEST/8) 			\
-		: base + (BTEOFF_DEST/8))
-
-#define BTE_CTRL_ADDR(base)					\
-    (is_shub2() ? base + (BTE2OFF_CTRL/8) 			\
-		: base + (BTEOFF_CTRL/8))
-
-#define BTE_NOTIF_ADDR(base)					\
-    (is_shub2() ? base + (BTE2OFF_NOTIFY/8) 			\
-		: base + (BTEOFF_NOTIFY/8))
-
-/* Define hardware modes */
-#define BTE_NOTIFY IBCT_NOTIFY
-#define BTE_NORMAL BTE_NOTIFY
-#define BTE_ZERO_FILL (BTE_NOTIFY | IBCT_ZFIL_MODE)
-/* Use a reserved bit to let the caller specify a wait for any BTE */
-#define BTE_WACQUIRE 0x4000
-/* Use the BTE on the node with the destination memory */
-#define BTE_USE_DEST (BTE_WACQUIRE << 1)
-/* Use any available BTE interface on any node for the transfer */
-#define BTE_USE_ANY (BTE_USE_DEST << 1)
-/* macro to force the IBCT0 value valid */
-#define BTE_VALID_MODE(x) ((x) & (IBCT_NOTIFY | IBCT_ZFIL_MODE))
-
-#define BTE_ACTIVE		(IBLS_BUSY | IBLS_ERROR)
-#define BTE_WORD_AVAILABLE	(IBLS_BUSY << 1)
-#define BTE_WORD_BUSY		(~BTE_WORD_AVAILABLE)
-
-/*
- * Some macros to simplify reading.
- * Start with macros to locate the BTE control registers.
- */
-#define BTE_LNSTAT_LOAD(_bte)						\
-			HUB_L(_bte->bte_base_addr)
-#define BTE_LNSTAT_STORE(_bte, _x)					\
-			HUB_S(_bte->bte_base_addr, (_x))
-#define BTE_SRC_STORE(_bte, _x)						\
-({									\
-		u64 __addr = ((_x) & ~AS_MASK);				\
-		if (is_shub2()) 					\
-			__addr = SH2_TIO_PHYS_TO_DMA(__addr);		\
-		HUB_S(_bte->bte_source_addr, __addr);			\
-})
-#define BTE_DEST_STORE(_bte, _x)					\
-({									\
-		u64 __addr = ((_x) & ~AS_MASK);				\
-		if (is_shub2()) 					\
-			__addr = SH2_TIO_PHYS_TO_DMA(__addr);		\
-		HUB_