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author | Qianggui Song <qianggui.song@amlogic.com> | 2019-12-16 20:36:44 +0800 |
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committer | Marc Zyngier <maz@kernel.org> | 2020-01-20 19:10:05 +0000 |
commit | 8f78bd62bdd7a7b0a9906c4827245bf17056f781 (patch) | |
tree | 3f02f189a43f017308bb6b9c2ffa5639c6b9d7ea /arch/arm | |
parent | e2514165f36edac382a95474a73ba2bfa51bc2b2 (diff) |
irqchip/meson-gpio: Add support for meson a1 SoCs
The meson a1 Socs have some changes compared with previous
chips. For A113L, it contains 62 pins and can be spied on:
- 62:128 undefined
- 61:50 12 pins on bank A
- 49:37 13 pins on bank F
- 36:20 17 pins on bank X
- 19:13 7 pins on bank B
- 12:0 13 pins on bank P
There are five relative registers for gpio interrupt controller,
details are as below:
- PADCTRL_GPIO_IRQ_CTRL0
bit[31]: enable/disable the whole irq lines
bit[16-23]: both edge trigger
bit[8-15]: single edge trigger
bit[0-7]: pol trigger
- PADCTRL_GPIO_IRQ_CTRL[X]
bit[0-6]: 7 bits to choose gpio source for irq line 2*[X] - 2
bit[16-22]: 7 bits to choose gpio source for irq line 2*[X] - 1
where X =1,2,3,4
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20191216123645.10099-4-qianggui.song@amlogic.com
Diffstat (limited to 'arch/arm')
0 files changed, 0 insertions, 0 deletions