diff options
| author | Olof Johansson <olof@lixom.net> | 2020-01-21 15:07:03 -0800 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2020-01-21 15:07:05 -0800 |
| commit | 31a7d26fbc51a39292bf9911f9e9efdf6d8e22b2 (patch) | |
| tree | 86e2727b9a3692552b977d8ba4da899e5f7f5353 /arch/arm | |
| parent | 21473e16b1161fd2f3c531c06efab5f7812e421a (diff) | |
| parent | 6c6b3f1f260b24dc0ab9cbbf369e4fa36819ab8b (diff) | |
Merge tag 'zynq-soc-for-v5.6' of https://github.com/Xilinx/linux-xlnx into arm/soc
ARM: Xilinx Zynq SoC patches for v5.6
- Fix cpuid handling logic in platform SMP startup code
* tag 'zynq-soc-for-v5.6' of https://github.com/Xilinx/linux-xlnx:
ARM: zynq: use physical cpuid in zynq_slcr_cpu_stop/start
Link: https://lore.kernel.org/r/50dec3cf-5f80-69be-c3d1-cc14b9bce5ff@monstr.eu
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-zynq/platsmp.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/mach-zynq/platsmp.c b/arch/arm/mach-zynq/platsmp.c index a10085be9073..68ec303fa278 100644 --- a/arch/arm/mach-zynq/platsmp.c +++ b/arch/arm/mach-zynq/platsmp.c @@ -15,6 +15,7 @@ #include <linux/init.h> #include <linux/io.h> #include <asm/cacheflush.h> +#include <asm/smp_plat.h> #include <asm/smp_scu.h> #include <linux/irqchip/arm-gic.h> #include "common.h" @@ -30,6 +31,7 @@ int zynq_cpun_start(u32 address, int cpu) { u32 trampoline_code_size = &zynq_secondary_trampoline_end - &zynq_secondary_trampoline; + u32 phy_cpuid = cpu_logical_map(cpu); /* MS: Expectation that SLCR are directly map and accessible */ /* Not possible to jump to non aligned address */ @@ -39,7 +41,7 @@ int zynq_cpun_start(u32 address, int cpu) u32 trampoline_size = &zynq_secondary_trampoline_jump - &zynq_secondary_trampoline; - zynq_slcr_cpu_stop(cpu); + zynq_slcr_cpu_stop(phy_cpuid); if (address) { if (__pa(PAGE_OFFSET)) { zero = ioremap(0, trampoline_code_size); @@ -68,7 +70,7 @@ int zynq_cpun_start(u32 address, int cpu) if (__pa(PAGE_OFFSET)) iounmap(zero); } - zynq_slcr_cpu_start(cpu); + zynq_slcr_cpu_start(phy_cpuid); return 0; } |