[ARM] 5532/1: Freescale STMP: register definitions [3/3]

Replace HW_zzz register access macros by regular __raw_readl/__raw_writel calls

Signed-off-by: dmitry pervushin <dpervushin@embeddedalley.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 64 insertions, 47 deletions

diff --git a/arch/arm/plat-stmp3xxx/timer.c b/arch/arm/plat-stmp3xxx/timer.c
index 7d872f0aee70..063c7bc0e740 100644
--- a/arch/arm/plat-stmp3xxx/timer.c
+++ b/arch/arm/plat-stmp3xxx/timer.c
@@ -26,6 +26,7 @@
 
 #include <asm/mach/time.h>
 #include <mach/stmp3xxx.h>
+#include <mach/platform.h>
 #include <mach/regs-timrot.h>
 
 static irqreturn_t
@@ -33,13 +34,22 @@ stmp3xxx_timer_interrupt(int irq, void *dev_id)
 {
 	struct clock_event_device *c = dev_id;
 
-	if (HW_TIMROT_TIMCTRLn_RD(0) & (1<<15)) {
-		HW_TIMROT_TIMCTRLn_CLR(0, (1<<15));
+	/* timer 0 */
+	if (__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0) &
+			BM_TIMROT_TIMCTRLn_IRQ) {
+		stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ,
+				REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
 		c->event_handler(c);
-	} else if (HW_TIMROT_TIMCTRLn_RD(1) & (1<<15)) {
-		HW_TIMROT_TIMCTRLn_CLR(1, (1<<15));
-		HW_TIMROT_TIMCTRLn_CLR(1, BM_TIMROT_TIMCTRLn_IRQ_EN);
-		HW_TIMROT_TIMCOUNTn_WR(1, 0xFFFF);
+	}
+
+	/* timer 1 */
+	else if (__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1)
+			& BM_TIMROT_TIMCTRLn_IRQ) {
+		stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ,
+				REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
+		stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ_EN,
+				REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
+		__raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
 	}
 
 	return IRQ_HANDLED;
@@ -47,14 +57,16 @@ stmp3xxx_timer_interrupt(int irq, void *dev_id)
 
 static cycle_t stmp3xxx_clock_read(struct clocksource *cs)
 {
-	return ~((HW_TIMROT_TIMCOUNTn_RD(1) & 0xFFFF0000) >> 16);
+	return ~((__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1)
+				& 0xFFFF0000) >> 16);
 }
 
 static int
 stmp3xxx_timrot_set_next_event(unsigned long delta,
 		struct clock_event_device *dev)
 {
-	HW_TIMROT_TIMCOUNTn_WR(0, delta); /* reload */
+	/* reload the timer */
+	__raw_writel(delta, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
 	return 0;
 }
 
@@ -102,25 +114,29 @@ static void __init stmp3xxx_init_timer(void)
 	ckevt_timrot.max_delta_ns = clockevent_delta2ns(0xFFF, &ckevt_timrot);
 	ckevt_timrot.cpumask = cpumask_of(0);
 
-	HW_TIMROT_ROTCTRL_CLR(BM_TIMROT_ROTCTRL_SFTRST |
-				BM_TIMROT_ROTCTRL_CLKGATE);
-	HW_TIMROT_TIMCOUNTn_WR(0, 0);
-	HW_TIMROT_TIMCOUNTn_WR(1, 0);
-
-	HW_TIMROT_TIMCTRLn_WR(0,
-			      (BF_TIMROT_TIMCTRLn_SELECT(8) |  /* 32 kHz */
-			       BF_TIMROT_TIMCTRLn_PRESCALE(0) |
-			       BM_TIMROT_TIMCTRLn_RELOAD |
-			       BM_TIMROT_TIMCTRLn_UPDATE |
-			       BM_TIMROT_TIMCTRLn_IRQ_EN));
-	HW_TIMROT_TIMCTRLn_WR(1,
-			      (BF_TIMROT_TIMCTRLn_SELECT(8) |  /* 32 kHz */
-			       BF_TIMROT_TIMCTRLn_PRESCALE(0) |
-			       BM_TIMROT_TIMCTRLn_RELOAD |
-			       BM_TIMROT_TIMCTRLn_UPDATE));
-
-	HW_TIMROT_TIMCOUNTn_WR(0, CLOCK_TICK_RATE / HZ - 1);
-	HW_TIMROT_TIMCOUNTn_WR(1, 0xFFFF); /* reload */
+	stmp3xxx_reset_block(REGS_TIMROT_BASE, false);
+
+	/* clear two timers */
+	__raw_writel(0, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
+	__raw_writel(0, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
+
+	/* configure them */
+	__raw_writel(
+		(8 << BP_TIMROT_TIMCTRLn_SELECT) |  /* 32 kHz */
+		BM_TIMROT_TIMCTRLn_RELOAD |
+		BM_TIMROT_TIMCTRLn_UPDATE |
+		BM_TIMROT_TIMCTRLn_IRQ_EN,
+			REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
+	__raw_writel(
+		(8 << BP_TIMROT_TIMCTRLn_SELECT) |  /* 32 kHz */
+		BM_TIMROT_TIMCTRLn_RELOAD |
+		BM_TIMROT_TIMCTRLn_UPDATE |
+		BM_TIMROT_TIMCTRLn_IRQ_EN,
+			REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
+
+	__raw_writel(CLOCK_TICK_RATE / HZ - 1,
+			REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
+	__raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
 
 	setup_irq(IRQ_TIMER0, &stmp3xxx_timer_irq);
 
@@ -132,30 +148,31 @@ static void __init stmp3xxx_init_timer(void)
 
 void stmp3xxx_suspend_timer(void)
 {
-	HW_TIMROT_TIMCTRLn_CLR(0, BM_TIMROT_TIMCTRLn_IRQ_EN);
-	HW_TIMROT_TIMCTRLn_CLR(0, (1<<15));
-	HW_TIMROT_ROTCTRL_SET(BM_TIMROT_ROTCTRL_CLKGATE);
+	stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ_EN | BM_TIMROT_TIMCTRLn_IRQ,
+			REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
+	stmp3xxx_setl(BM_TIMROT_ROTCTRL_CLKGATE,
+			REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL);
 }
 
 void stmp3xxx_resume_timer(void)
 {
-	HW_TIMROT_ROTCTRL_CLR(BM_TIMROT_ROTCTRL_SFTRST |
-				BM_TIMROT_ROTCTRL_CLKGATE);
-
-
-	HW_TIMROT_TIMCTRLn_WR(0,
-			      (BF_TIMROT_TIMCTRLn_SELECT(8) |  /* 32 kHz */
-			       BF_TIMROT_TIMCTRLn_PRESCALE(0) |
-			       BM_TIMROT_TIMCTRLn_UPDATE |
-			       BM_TIMROT_TIMCTRLn_IRQ_EN));
-	HW_TIMROT_TIMCTRLn_WR(1,
-			      (BF_TIMROT_TIMCTRLn_SELECT(8) |  /* 32 kHz */
-			       BF_TIMROT_TIMCTRLn_PRESCALE(0) |
-			       BM_TIMROT_TIMCTRLn_RELOAD |
-			       BM_TIMROT_TIMCTRLn_UPDATE));
-
-	HW_TIMROT_TIMCOUNTn_WR(0, CLOCK_TICK_RATE / HZ - 1);
-	HW_TIMROT_TIMCOUNTn_WR(1, 0xFFFF); /* reload */
+	stmp3xxx_clearl(BM_TIMROT_ROTCTRL_SFTRST | BM_TIMROT_ROTCTRL_CLKGATE,
+			REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL);
+	__raw_writel(
+		8 << BP_TIMROT_TIMCTRLn_SELECT |  /* 32 kHz */
+		BM_TIMROT_TIMCTRLn_RELOAD |
+		BM_TIMROT_TIMCTRLn_UPDATE |
+		BM_TIMROT_TIMCTRLn_IRQ_EN,
+			REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
+	__raw_writel(
+		8 << BP_TIMROT_TIMCTRLn_SELECT |  /* 32 kHz */
+		BM_TIMROT_TIMCTRLn_RELOAD |
+		BM_TIMROT_TIMCTRLn_UPDATE |
+		BM_TIMROT_TIMCTRLn_IRQ_EN,
+			REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
+	__raw_writel(CLOCK_TICK_RATE / HZ - 1,
+			REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
+	__raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
 }
 
 #else