diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2013-02-21 15:27:22 -0800 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2013-02-21 15:27:22 -0800 |
commit | bab588fcfb6335c767d811a8955979f5440328e0 (patch) | |
tree | 2a862ddf47a82be885a8e7945a17cc3ff7a658b9 /arch/arm/mach-tegra | |
parent | 3298a3511f1e73255a8dc023efd909e569eea037 (diff) | |
parent | 9cb0d1babfcb1b4ac248c09425f7d5de1e771133 (diff) |
Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC-specific updates from Arnd Bergmann:
"This is a larger set of new functionality for the existing SoC
families, including:
- vt8500 gains support for new CPU cores, notably the Cortex-A9 based
wm8850
- prima2 gains support for the "marco" SoC family, its SMP based
cousin
- tegra gains support for the new Tegra4 (Tegra114) family
- socfpga now supports a newer version of the hardware including SMP
- i.mx31 and bcm2835 are now using DT probing for their clocks
- lots of updates for sh-mobile
- OMAP updates for clocks, power management and USB
- i.mx6q and tegra now support cpuidle
- kirkwood now supports PCIe hot plugging
- tegra clock support is updated
- tegra USB PHY probing gets implemented diffently"
* tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (148 commits)
ARM: prima2: remove duplicate v7_invalidate_l1
ARM: shmobile: r8a7779: Correct TMU clock support again
ARM: prima2: fix __init section for cpu hotplug
ARM: OMAP: Consolidate OMAP USB-HS platform data (part 3/3)
ARM: OMAP: Consolidate OMAP USB-HS platform data (part 1/3)
arm: socfpga: Add SMP support for actual socfpga harware
arm: Add v7_invalidate_l1 to cache-v7.S
arm: socfpga: Add entries to enable make dtbs socfpga
arm: socfpga: Add new device tree source for actual socfpga HW
ARM: tegra: sort Kconfig selects for Tegra114
ARM: tegra: enable ARCH_REQUIRE_GPIOLIB for Tegra114
ARM: tegra: Fix build error w/ ARCH_TEGRA_114_SOC w/o ARCH_TEGRA_3x_SOC
ARM: tegra: Fix build error for gic update
ARM: tegra: remove empty tegra_smp_init_cpus()
ARM: shmobile: Register ARM architected timer
ARM: MARCO: fix the build issue due to gic-vic-to-irqchip move
ARM: shmobile: r8a7779: Correct TMU clock support
ARM: mxs_defconfig: Select CONFIG_DEVTMPFS_MOUNT
ARM: mxs: decrease mxs_clockevent_device.min_delta_ns to 2 clock cycles
ARM: mxs: use apbx bus clock to drive the timers on timrotv2
...
Diffstat (limited to 'arch/arm/mach-tegra')
39 files changed, 690 insertions, 7545 deletions
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 1ec7f80e2af5..d1c4893894ce 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -4,7 +4,7 @@ comment "NVIDIA Tegra options" config ARCH_TEGRA_2x_SOC bool "Enable support for Tegra20 family" - select ARCH_REQUIRE_GPIOLIB + select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP select ARM_ERRATA_720789 select ARM_ERRATA_742230 if SMP select ARM_ERRATA_751472 @@ -26,7 +26,6 @@ config ARCH_TEGRA_2x_SOC config ARCH_TEGRA_3x_SOC bool "Enable support for Tegra30 family" - select ARCH_REQUIRE_GPIOLIB select ARM_ERRATA_743622 select ARM_ERRATA_751472 select ARM_ERRATA_754322 @@ -44,6 +43,18 @@ config ARCH_TEGRA_3x_SOC Support for NVIDIA Tegra T30 processor family, based on the ARM CortexA9MP CPU and the ARM PL310 L2 cache controller +config ARCH_TEGRA_114_SOC + bool "Enable support for Tegra114 family" + select ARM_ARCH_TIMER + select ARM_GIC + select ARM_L1_CACHE_SHIFT_6 + select CPU_V7 + select PINCTRL + select PINCTRL_TEGRA114 + help + Support for NVIDIA Tegra T114 processor family, based on the + ARM CortexA15MP CPU + config TEGRA_PCI bool "PCI Express support" depends on ARCH_TEGRA_2x_SOC diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index f0520961bafe..f6b46ae2b7f8 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -1,7 +1,6 @@ obj-y += common.o obj-y += io.o obj-y += irq.o -obj-y += clock.o obj-y += fuse.o obj-y += pmc.o obj-y += flowctrl.o @@ -12,16 +11,12 @@ obj-y += reset.o obj-y += reset-handler.o obj-y += sleep.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o -obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks.o -obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks_data.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_speedo.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-tegra20.o ifeq ($(CONFIG_CPU_IDLE),y) obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += cpuidle-tegra20.o endif -obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o -obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks_data.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_speedo.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-tegra30.o ifeq ($(CONFIG_CPU_IDLE),y) @@ -34,6 +29,10 @@ obj-$(CONFIG_TEGRA_PCI) += pcie.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-dt-tegra20.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o +obj-$(CONFIG_ARCH_TEGRA_114_SOC) += board-dt-tegra114.o +ifeq ($(CONFIG_CPU_IDLE),y) +obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o +endif obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-harmony-pcie.o diff --git a/arch/arm/mach-tegra/board-dt-tegra114.c b/arch/arm/mach-tegra/board-dt-tegra114.c new file mode 100644 index 000000000000..085d63637b62 --- /dev/null +++ b/arch/arm/mach-tegra/board-dt-tegra114.c @@ -0,0 +1,46 @@ +/* + * NVIDIA Tegra114 device tree board support + * + * Copyright (C) 2013 NVIDIA Corporation + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/of.h> +#include <linux/of_platform.h> +#include <linux/clocksource.h> + +#include <asm/mach/arch.h> + +#include "board.h" +#include "common.h" + +static void __init tegra114_dt_init(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} + +static const char * const tegra114_dt_board_compat[] = { + "nvidia,tegra114", + NULL, +}; + +DT_MACHINE_START(TEGRA114_DT, "NVIDIA Tegra114 (Flattened Device Tree)") + .smp = smp_ops(tegra_smp_ops), + .map_io = tegra_map_common_io, + .init_early = tegra114_init_early, + .init_irq = tegra_dt_init_irq, + .init_time = clocksource_of_init, + .init_machine = tegra114_dt_init, + .init_late = tegra_init_late, + .restart = tegra_assert_system_reset, + .dt_compat = tegra114_dt_board_compat, +MACHINE_END diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c index d320f7ad7350..a0edf2510280 100644 --- a/arch/arm/mach-tegra/board-dt-tegra20.c +++ b/arch/arm/mach-tegra/board-dt-tegra20.c @@ -40,7 +40,6 @@ #include <asm/setup.h> #include "board.h" -#include "clock.h" #include "common.h" #include "iomap.h" @@ -69,70 +68,17 @@ static struct tegra_ehci_platform_data tegra_ehci3_pdata = { }; static struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC1_BASE, "sdhci-tegra.0", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC2_BASE, "sdhci-tegra.1", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC3_BASE, "sdhci-tegra.2", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-sdhci", TEGRA_SDMMC4_BASE, "sdhci-tegra.3", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C_BASE, "tegra-i2c.0", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C2_BASE, "tegra-i2c.1", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-i2c", TEGRA_I2C3_BASE, "tegra-i2c.2", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-i2c-dvc", TEGRA_DVC_BASE, "tegra-i2c.3", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S1_BASE, "tegra20-i2s.0", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-i2s", TEGRA_I2S2_BASE, "tegra20-i2s.1", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-das", TEGRA_APB_MISC_DAS_BASE, "tegra20-das", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB_BASE, "tegra-ehci.0", + OF_DEV_AUXDATA("nvidia,tegra20-ehci", 0xC5000000, "tegra-ehci.0", &tegra_ehci1_pdata), - OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB2_BASE, "tegra-ehci.1", + OF_DEV_AUXDATA("nvidia,tegra20-ehci", 0xC5004000, "tegra-ehci.1", &tegra_ehci2_pdata), - OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB3_BASE, "tegra-ehci.2", + OF_DEV_AUXDATA("nvidia,tegra20-ehci", 0xC5008000, "tegra-ehci.2", &tegra_ehci3_pdata), - OF_DEV_AUXDATA("nvidia,tegra20-apbdma", TEGRA_APB_DMA_BASE, "tegra-apbdma", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-sflash", 0x7000c380, "spi", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D400, "spi_tegra.0", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D600, "spi_tegra.1", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D800, "spi_tegra.2", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000DA00, "spi_tegra.3", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-host1x", 0x50000000, "host1x", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-dc", 0x54200000, "tegradc.0", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-dc", 0x54240000, "tegradc.1", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-hdmi", 0x54280000, "hdmi", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-dsi", 0x54300000, "dsi", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-tvo", 0x542c0000, "tvo", NULL), {} }; -static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = { - /* name parent rate enabled */ - { "uarta", "pll_p", 216000000, true }, - { "uartd", "pll_p", 216000000, true }, - { "usbd", "clk_m", 12000000, false }, - { "usb2", "clk_m", 12000000, false }, - { "usb3", "clk_m", 12000000, false }, - { "pll_a", "pll_p_out1", 56448000, true }, - { "pll_a_out0", "pll_a", 11289600, true }, - { "cdev1", NULL, 0, true }, - { "blink", "clk_32k", 32768, true }, - { "i2s1", "pll_a_out0", 11289600, false}, - { "i2s2", "pll_a_out0", 11289600, false}, - { "sdmmc1", "pll_p", 48000000, false}, - { "sdmmc3", "pll_p", 48000000, false}, - { "sdmmc4", "pll_p", 48000000, false}, - { "spi", "pll_p", 20000000, false }, - { "sbc1", "pll_p", 100000000, false }, - { "sbc2", "pll_p", 100000000, false }, - { "sbc3", "pll_p", 100000000, false }, - { "sbc4", "pll_p", 100000000, false }, - { "host1x", "pll_c", 150000000, false }, - { "disp1", "pll_p", 600000000, false }, - { "disp2", "pll_p", 600000000, false }, - { NULL, NULL, 0, 0}, -}; - static void __init tegra_dt_init(void) { - tegra_clk_init_from_table(tegra_dt_clk_init_table); - /* * Finished with the static registrations now; fill in the missing * devices diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c index 97e1f67fc31d..bf68567e549d 100644 --- a/arch/arm/mach-tegra/board-dt-tegra30.c +++ b/arch/arm/mach-tegra/board-dt-tegra30.c @@ -34,72 +34,12 @@ #include <asm/mach/arch.h> #include "board.h" -#include "clock.h" #include "common.h" #include "iomap.h" -static struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = { - OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000000, "sdhci-tegra.0", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000200, "sdhci-tegra.1", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000400, "sdhci-tegra.2", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000600, "sdhci-tegra.3", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C000, "tegra-i2c.0", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C400, "tegra-i2c.1", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C500, "tegra-i2c.2", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C700, "tegra-i2c.3", NULL), - OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000D000, "tegra-i2c.4", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-ahub", 0x70080000, "tegra30-ahub", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-apbdma", 0x6000a000, "tegra-apbdma", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D400, "spi_tegra.0", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D600, "spi_tegra.1", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D800, "spi_tegra.2", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DA00, "spi_tegra.3", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DC00, "spi_tegra.4", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DE00, "spi_tegra.5", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-host1x", 0x50000000, "host1x", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-dc", 0x54200000, "tegradc.0", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-dc", 0x54240000, "tegradc.1", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-hdmi", 0x54280000, "hdmi", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-dsi", 0x54300000, "dsi", NULL), - OF_DEV_AUXDATA("nvidia,tegra30-tvo", 0x542c0000, "tvo", NULL), - {} -}; - -static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = { - /* name parent rate enabled */ - { "uarta", "pll_p", 408000000, true }, - { "pll_a", "pll_p_out1", 564480000, true }, - { "pll_a_out0", "pll_a", 11289600, true }, - { "extern1", "pll_a_out0", 0, true }, - { "clk_out_1", "extern1", 0, true }, - { "blink", "clk_32k", 32768, true }, - { "i2s0", "pll_a_out0", 11289600, false}, - { "i2s1", "pll_a_out0", 11289600, false}, - { "i2s2", "pll_a_out0", 11289600, false}, - { "i2s3", "pll_a_out0", 11289600, false}, - { "i2s4", "pll_a_out0", 11289600, false}, - { "sdmmc1", "pll_p", 48000000, false}, - { "sdmmc3", "pll_p", 48000000, false}, - { "sdmmc4", "pll_p", 48000000, false}, - { "sbc1", "pll_p", 100000000, false}, - { "sbc2", "pll_p", 100000000, false}, - { "sbc3", "pll_p", 100000000, false}, - { "sbc4", "pll_p", 100000000, false}, - { "sbc5", "pll_p", 100000000, false}, - { "sbc6", "pll_p", 100000000, false}, - { "host1x", "pll_c", 150000000, false}, - { "disp1", "pll_p", 600000000, false}, - { "disp2", "pll_p", 600000000, false}, - { NULL, NULL, 0, 0}, -}; - static void __init tegra30_dt_init(void) { - tegra_clk_init_from_table(tegra_dt_clk_init_table); - - of_platform_populate(NULL, of_default_bus_match_table, - tegra30_auxdata_lookup, NULL); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } static const char *tegra30_dt_board_compat[] = { diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h index da8f5a3c4240..86851c81a350 100644 --- a/arch/arm/mach-tegra/board.h +++ b/arch/arm/mach-tegra/board.h @@ -1,6 +1,7 @@ /* * arch/arm/mach-tegra/board.h * + * Copyright (c) 2013 NVIDIA Corporation. All rights reserved. * Copyright (C) 2010 Google, Inc. * * Author: @@ -27,6 +28,7 @@ void tegra_assert_system_reset(char mode, const char *cmd); void __init tegra20_init_early(void); void __init tegra30_init_early(void); +void __init tegra114_init_early(void); void __init tegra_map_common_io(void); void __init tegra_init_irq(void); void __init tegra_dt_init_irq(void); diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c deleted file mode 100644 index 867bf8bf5561..000000000000 --- a/arch/arm/mach-tegra/clock.c +++ /dev/null @@ -1,166 +0,0 @@ -/* - * - * Copyright (C) 2010 Google, Inc. - * Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved. - * - * Author: - * Colin Cross <ccross@google.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <linux/kernel.h> -#include <linux/clk.h> -#include <linux/clkdev.h> -#include <linux/init.h> -#include <linux/list.h> -#include <linux/module.h> -#include <linux/sched.h> -#include <linux/seq_file.h> -#include <linux/slab.h> - -#include "board.h" -#include "clock.h" -#include "tegra_cpu_car.h" - -/* Global data of Tegra CPU CAR ops */ -struct tegra_cpu_car_ops *tegra_cpu_car_ops; - -/* - * Locking: - * - * An additional mutex, clock_list_lock, is used to protect the list of all - * clocks. - * - */ -static DEFINE_MUTEX(clock_list_lock); -static LIST_HEAD(clocks); - -void tegra_clk_add(struct clk *clk) -{ - struct clk_tegra *c = to_clk_tegra(__clk_get_hw(clk)); - - mutex_lock(&clock_list_lock); - list_add(&c->node, &clocks); - mutex_unlock(&clock_list_lock); -} - -struct clk *tegra_get_clock_by_name(const char *name) -{ - struct clk_tegra *c; - struct clk *ret = NULL; - mutex_lock(&clock_list_lock); - list_for_each_entry(c, &clocks, node) { - if (strcmp(__clk_get_name(c->hw.clk), name) == 0) { - ret = c->hw.clk; - break; - } - } - mutex_unlock(&clock_list_lock); - return ret; -} - -static int tegra_clk_init_one_from_table(struct tegra_clk_init_table *table) -{ - struct clk *c; - struct clk *p; - struct clk *parent; - - int ret = 0; - - c = tegra_get_clock_by_name(table->name); - - if (!c) { - pr_warn("Unable to initialize clock %s\n", - table->name); - return -ENODEV; - } - - parent = clk_get_parent(c); - - if (table->parent) { - p = tegra_get_clock_by_name(table->parent); - if (!p) { - pr_warn("Unable to find parent %s of clock %s\n", - table->parent, table->name); - return -ENODEV; - } - - if (parent != p) { - ret = clk_set_parent(c, p); - if (ret) { - pr_warn("Unable to set parent %s of clock %s: %d\n", - table->parent, table->name, ret); - return -EINVAL; - } - } - } - - if (table->rate && table->rate != clk_get_rate(c)) { - ret = clk_set_rate(c, table->rate); - if (ret) { - pr_warn("Unable to set clock %s to rate %lu: %d\n", - table->name, table->rate, ret); - return -EINVAL; - } - } - - if (table->enabled) { - ret = clk_prepare_enable(c); - if (ret) { - pr_warn("Unable to enable clock %s: %d\n", - table->name, ret); - return -EINVAL; - } - } - - return 0; -} - -void tegra_clk_init_from_table(struct tegra_clk_init_table *table) -{ - for (; table->name; table++) - tegra_clk_init_one_from_table(table); -} - -void tegra_periph_reset_deassert(struct clk *c) -{ - struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c)); - BUG_ON(!clk->reset); - clk->reset(__clk_get_hw(c), false); -} -EXPORT_SYMBOL(tegra_periph_reset_deassert); - -void tegra_periph_reset_assert(struct clk *c) -{ - struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c)); - BUG_ON(!clk->reset); - clk->reset(__clk_get_hw(c), true); -} -EXPORT_SYMBOL(tegra_periph_reset_assert); - -/* Several extended clock configuration bits (e.g., clock routing, clock - * phase control) are included in PLL and peripheral clock source - * registers. */ -int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting) -{ - int ret = 0; - struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c)); - - if (!clk->clk_cfg_ex) { - ret = -ENOSYS; - goto out; - } - ret = clk->clk_cfg_ex(__clk_get_hw(c), p, setting); - -out: - return ret; -} diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h deleted file mode 100644 index 2aa37f5c44c0..000000000000 --- a/arch/arm/mach-tegra/clock.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - * arch/arm/mach-tegra/include/mach/clock.h - * - * Copyright (C) 2010 Google, Inc. - * Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved. - * - * Author: - * Colin Cross <ccross@google.com> - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __MACH_TEGRA_CLOCK_H -#define __MACH_TEGRA_CLOCK_H - -#include <linux/clk-provider.h> -#include <linux/clkdev.h> -#include <linux/list.h> - -#include <mach/clk.h> - -#define DIV_BUS (1 << 0) -#define DIV_U71 (1 << 1) -#define DIV_U71_FIXED (1 << 2) -#define DIV_2 (1 << 3) -#define DIV_U16 (1 << 4) -#define PLL_FIXED (1 << 5) -#define PLL_HAS_CPCON (1 << 6) -#define MUX (1 << 7) -#define PLLD (1 << 8) -#define PERIPH_NO_RESET (1 << 9) -#define PERIPH_NO_ENB (1 << 10) -#define PERIPH_EMC_ENB (1 << 11) -#define PERIPH_MANUAL_RESET (1 << 12) -#define PLL_ALT_MISC_REG (1 << 13) -#define PLLU (1 << 14) -#define PLLX (1 << 15) -#define MUX_PWM (1 << 16) -#define MUX8 (1 << 17) -#define DIV_U71_UART (1 << 18) -#define MUX_CLK_OUT (1 << 19) -#define PLLM (1 << 20) -#define DIV_U71_INT (1 << 21) -#define DIV_U71_IDLE (1 << 22) -#define ENABLE_ON_INIT (1 << 28) -#define PERIPH_ON_APB (1 << 29) - -struct clk_tegra; -#define to_clk_tegra(_hw) container_of(_hw, struct clk_tegra, hw) - -struct clk_mux_sel { - struct clk *input; - u32 value; -}; - -struct clk_pll_freq_table { - unsigned long input_rate; - unsigned long output_rate; - u16 n; - u16 m; - u8 p; - u8 cpcon; -}; - -enum clk_state { - UNINITIALIZED = 0, - ON, - OFF, -}; - -struct clk_tegra { - /* node for master clocks list */ - struct list_head node; /* node for list of all clocks */ - struct clk_lookup lookup; - struct clk_hw hw; - - bool set; - unsigned long fixed_rate; - unsigned long max_rate; - unsigned long min_rate; - u32 flags; - const char *name; - - enum clk_state state; - u32 div; - u32 mul; - - u32 reg; - u32 reg_shift; - - struct list_head shared_bus_list; - - union { - struct { - unsigned int clk_num; - } periph; - struct { - unsigned long input_min; - unsigned long input_max; - unsigned long cf_min; - unsigned long cf_max; - unsigned long vco_min; - unsigned long vco_max; - const struct clk_pll_freq_table *freq_table; - int lock_delay; - unsigned long fixed_rate; - } pll; - struct { - u32 sel; - u32 reg_mask; - } mux; - struct { - struct clk *main; - struct clk *backup; - } cpu; - struct { - struct list_head node; - bool enabled; - unsigned long rate; - } shared_bus_user; - } u; - - void (*reset)(struct clk_hw *, bool); - int (*clk_cfg_ex)(struct clk_hw *, enum tegra_clk_ex_param, u32); -}; - -struct clk_duplicate { - const char *name; - struct clk_lookup lookup; -}; - -struct tegra_clk_init_table { - const char *name; - const char *parent; - unsigned long rate; - bool enabled; -}; - -void tegra_clk_add(struct clk *c); -void tegra2_init_clocks(void); -void tegra30_init_clocks(void); -struct clk *tegra_get_clock_by_name(const char *name); -void tegra_clk_init_from_table(struct tegra_clk_init_table *table); - -#endif diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 8f0ffe97ffee..5449a3f2977b 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -1,6 +1,7 @@ /* * arch/arm/mach-tegra/common.c * + * Copyright (c) 2013 NVIDIA Corporation. All rights reserved. * Copyright (C) 2010 Google, Inc. * * Author: @@ -22,13 +23,13 @@ #include <linux/clk.h> #include <linux/delay.h> #include <linux/irqchip.h> +#include <linux/clk/tegra.h> #include <asm/hardware/cache-l2x0.h> #include <mach/powergate.h> #include "board.h" -#include "clock.h" #include "common.h" #include "fuse.h" #include "iomap.h" @@ -59,6 +60,7 @@ u32 tegra_uart_config[4] = { #ifdef CONFIG_OF void __init tegra_dt_init_irq(void) { + tegra_clocks_init(); tegra_init_irq(); irqchip_init(); } @@ -74,43 +76,6 @@ void tegra_assert_system_reset(char mode, const char *cmd) writel_relaxed(reg, reset); } -#ifdef CONFIG_ARCH_TEGRA_2x_SOC -static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = { - /* name parent rate enabled */ - { "clk_m", NULL, 0, true }, - { "pll_p", "clk_m", 216000000, true }, - { "pll_p_out1", "pll_p", 28800000, true }, - { "pll_p_out2", "pll_p", 48000000, true }, - { "pll_p_out3", "pll_p", 72000000, true }, - { "pll_p_out4", "pll_p", 24000000, true }, - { "pll_c", "clk_m", 600000000, true }, - { "pll_c_out1", "pll_c", 120000000, true }, - { "sclk", "pll_c_out1", 120000000, true }, - { "hclk", "sclk", 120000000, true }, - { "pclk", "hclk", 60000000, true }, - { "csite", NULL, 0, true }, - { "emc", NULL, 0, true }, - { "cpu", NULL, 0, true }, - { NULL, NULL, 0, 0}, -}; -#endif - -#ifdef CONFIG_ARCH_TEGRA_3x_SOC -static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = { - /* name parent rate enabled */ - { "clk_m", NULL, 0, true }, - { "pll_p", "pll_ref", 408000000, true }, - { "pll_p_out1", "pll_p", 9600000, true }, - { "pll_p_out4", "pll_p", 102000000, true }, - { "sclk", "pll_p_out4", 102000000, true }, - { "hclk", "sclk", 102000000, true }, - { "pclk", "hclk", 51000000, true }, - { "csite", NULL, 0, true }, - { NULL, NULL, 0, 0}, -}; -#endif - - static void __init tegra_init_cache(void) { #ifdef CONFIG_CACHE_L2X0 |