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authorAnson Huang <b20788@freescale.com>2014-09-17 11:11:45 +0800
committerShawn Guo <shawn.guo@linaro.org>2014-11-23 14:56:17 +0800
commitec336b284136610a43c9daac56d66b20d43ddf7b (patch)
tree83577860847dac802631c097be8aefdd8b28ac96 /arch/arm/mach-imx/mxc.h
parent035d0d7830b180215f0779d1b6dfb210f33a49fe (diff)
ARM: imx: replace cpu type check with ddr type check
As the DDR/IO and MMDC setting are different on LPDDR2 and DDR3, we used cpu type to decide how to do these settings in suspend before which is NOT flexible, take i.MX6SL for example, although it has LPDDR2 on EVK board, but users can also use DDR3 on other boards, so it is better to read the DDR type from MMDC then decide how to do related settings. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'arch/arm/mach-imx/mxc.h')
-rw-r--r--arch/arm/mach-imx/mxc.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h
index 17a41ca65acf..4c1343df2ba4 100644
--- a/arch/arm/mach-imx/mxc.h
+++ b/arch/arm/mach-imx/mxc.h
@@ -55,6 +55,8 @@
#define IMX_CHIP_REVISION_3_3 0x33
#define IMX_CHIP_REVISION_UNKNOWN 0xff
+#define IMX_DDR_TYPE_LPDDR2 1
+
#ifndef __ASSEMBLY__
extern unsigned int __mxc_cpu_type;
#endif