diff options
author | Saeed Bishara <saeed@marvell.com> | 2009-08-06 15:12:43 +0300 |
---|---|---|
committer | Nicolas Pitre <nico@fluxnic.net> | 2009-11-27 15:43:06 -0500 |
commit | edabd38e1a017e922e3e3b485ee3ddb4df433aa4 (patch) | |
tree | c79cef3e59f62014c12ff1203e84b0bac5610a55 /arch/arm/mach-dove | |
parent | 8d27b2f7988b652dbabf79291a3e2550c06e1af5 (diff) |
ARM: add base support for Marvell Dove SoC
The Marvell Dove (88AP510) is a high-performance, highly integrated,
low power SoC with high-end ARM-compatible processor (known as PJ4),
graphics processing unit, high-definition video decoding acceleration
hardware, and a broad range of peripherals.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Diffstat (limited to 'arch/arm/mach-dove')
23 files changed, 2103 insertions, 0 deletions
diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig new file mode 100644 index 000000000000..3b9a32ace909 --- /dev/null +++ b/arch/arm/mach-dove/Kconfig @@ -0,0 +1,14 @@ +if ARCH_DOVE + +menu "Marvell Dove Implementations" + +config MACH_DOVE_DB + bool "Marvell DB-MV88AP510 Development Board" + select I2C_BOARDINFO + help + Say 'Y' here if you want your kernel to support the + Marvell DB-MV88AP510 Development Board. + +endmenu + +endif diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile new file mode 100644 index 000000000000..7ab3be53f642 --- /dev/null +++ b/arch/arm/mach-dove/Makefile @@ -0,0 +1,3 @@ +obj-y += common.o addr-map.o irq.o pcie.o + +obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o diff --git a/arch/arm/mach-dove/Makefile.boot b/arch/arm/mach-dove/Makefile.boot new file mode 100644 index 000000000000..67039c3e0c48 --- /dev/null +++ b/arch/arm/mach-dove/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0x00008000 +params_phys-y := 0x00000100 +initrd_phys-y := 0x00800000 diff --git a/arch/arm/mach-dove/addr-map.c b/arch/arm/mach-dove/addr-map.c new file mode 100644 index 000000000000..00be4fc26dd7 --- /dev/null +++ b/arch/arm/mach-dove/addr-map.c @@ -0,0 +1,149 @@ +/* + * arch/arm/mach-dove/addr-map.c + * + * Address map functions for Marvell Dove 88AP510 SoC + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/mbus.h> +#include <linux/io.h> +#include <asm/mach/arch.h> +#include <asm/setup.h> +#include "common.h" + +/* + * Generic Address Decode Windows bit settings + */ +#define TARGET_DDR 0x0 +#define TARGET_BOOTROM 0x1 +#define TARGET_CESA 0x3 +#define TARGET_PCIE0 0x4 +#define TARGET_PCIE1 0x8 +#define TARGET_SCRATCHPAD 0xd + +#define ATTR_CESA 0x01 +#define ATTR_BOOTROM 0xfd +#define ATTR_DEV_SPI0_ROM 0xfe +#define ATTR_DEV_SPI1_ROM 0xfb +#define ATTR_PCIE_IO 0xe0 +#define ATTR_PCIE_MEM 0xe8 +#define ATTR_SCRATCHPAD 0x0 + +/* + * CPU Address Decode Windows registers + */ +#define WIN_CTRL(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x0) +#define WIN_BASE(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x4) +#define WIN_REMAP_LO(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x8) +#define WIN_REMAP_HI(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0xc) + +struct mbus_dram_target_info dove_mbus_dram_info; + +static inline void __iomem *ddr_map_sc(int i) +{ + return (void __iomem *)(DOVE_MC_VIRT_BASE + 0x100 + ((i) << 4)); +} + +static int cpu_win_can_remap(int win) +{ + if (win < 4) + return 1; + + return 0; +} + +static void __init setup_cpu_win(int win, u32 base, u32 size, + u8 target, u8 attr, int remap) +{ + u32 ctrl; + + base &= 0xffff0000; + ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1; + + writel(base, WIN_BASE(win)); + writel(ctrl, WIN_CTRL(win)); + if (cpu_win_can_remap(win)) { + if (remap < 0) + remap = base; + writel(remap & 0xffff0000, WIN_REMAP_LO(win)); + writel(0, WIN_REMAP_HI(win)); + } +} + +void __init dove_setup_cpu_mbus(void) +{ + int i; + int cs; + + /* + * First, disable and clear windows. + */ + for (i = 0; i < 8; i++) { + writel(0, WIN_BASE(i)); + writel(0, WIN_CTRL(i)); + if (cpu_win_can_remap(i)) { + writel(0, WIN_REMAP_LO(i)); + writel(0, WIN_REMAP_HI(i)); + } + } + + /* + * Setup windows for PCIe IO+MEM space. + */ + setup_cpu_win(0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE, + TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE); + setup_cpu_win(1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE, + TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE); + setup_cpu_win(2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE, + TARGET_PCIE0, ATTR_PCIE_MEM, -1); + setup_cpu_win(3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE, + TARGET_PCIE1, ATTR_PCIE_MEM, -1); + + /* + * Setup window for CESA engine. + */ + setup_cpu_win(4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE, + TARGET_CESA, ATTR_CESA, -1); + + /* + * Setup the Window to the BootROM for Standby and Sleep Resume + */ + setup_cpu_win(5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE, + TARGET_BOOTROM, ATTR_BOOTROM, -1); + + /* + * Setup the Window to the PMU Scratch Pad space + */ + setup_cpu_win(6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE, + TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1); + + /* + * Setup MBUS dram target info. + */ + dove_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; + + for (i = 0, cs = 0; i < 2; i++) { + u32 map = readl(ddr_map_sc(i)); + + /* + * Chip select enabled? + */ + if (map & 1) { + struct mbus_dram_window *w; + + w = &dove_mbus_dram_info.cs[cs++]; + w->cs_index = i; + w->mbus_attr = 0; /* CS address decoding done inside */ + /* the DDR controller, no need to */ + /* provide attributes */ + w->base = map & 0xff800000; + w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4); + } + } + dove_mbus_dram_info.num_cs = cs; +} diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c new file mode 100644 index 000000000000..a20cf099cd97 --- /dev/null +++ b/arch/arm/mach-dove/common.c @@ -0,0 +1,777 @@ +/* + * arch/arm/mach-dove/common.c + * + * Core functions for Marvell Dove 88AP510 System On Chip + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/delay.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/pci.h> +#include <linux/serial_8250.h> +#include <linux/clk.h> +#include <linux/mbus.h> +#include <linux/mv643xx_eth.h> +#include <linux/mv643xx_i2c.h> +#include <linux/ata_platform.h> +#include <linux/spi/orion_spi.h> +#include <linux/gpio.h> +#include <asm/page.h> +#include <asm/setup.h> +#include <asm/timex.h> +#include <asm/mach/map.h> +#include <asm/mach/time.h> +#include <asm/mach/pci.h> +#include <mach/dove.h> +#include <mach/bridge-regs.h> +#include <asm/mach/arch.h> +#include <linux/irq.h> +#include <plat/mv_xor.h> +#include <plat/ehci-orion.h> +#include <plat/time.h> +#include "common.h" + +/***************************************************************************** + * I/O Address Mapping + ****************************************************************************/ +static struct map_desc dove_io_desc[] __initdata = { + { + .virtual = DOVE_SB_REGS_VIRT_BASE, + .pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE), + .length = DOVE_SB_REGS_SIZE, + .type = MT_DEVICE, + }, { + .virtual = DOVE_NB_REGS_VIRT_BASE, + .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE), + .length = DOVE_NB_REGS_SIZE, + .type = MT_DEVICE, + }, { + .virtual = DOVE_PCIE0_IO_VIRT_BASE, + .pfn = __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE), + .length = DOVE_PCIE0_IO_SIZE, + .type = MT_DEVICE, + }, { + .virtual = DOVE_PCIE1_IO_VIRT_BASE, + .pfn = __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE), + .length = DOVE_PCIE1_IO_SIZE, + .type = MT_DEVICE, + }, +}; + +void __init dove_map_io(void) +{ + iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc)); +} + +/***************************************************************************** + * EHCI + ****************************************************************************/ +static struct orion_ehci_data dove_ehci_data = { + .dram = &dove_mbus_dram_info, + .phy_version = EHCI_PHY_NA, +}; + +static u64 ehci_dmamask = DMA_BIT_MASK(32); + +/***************************************************************************** + * EHCI0 + ****************************************************************************/ +static struct resource dove_ehci0_resources[] = { + { + .start = DOVE_USB0_PHYS_BASE, + .end = DOVE_USB0_PHYS_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_DOVE_USB0, + .end = IRQ_DOVE_USB0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dove_ehci0 = { + .name = "orion-ehci", + .id = 0, + .dev = { + .dma_mask = &ehci_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &dove_ehci_data, + }, + .resource = dove_ehci0_resources, + .num_resources = ARRAY_SIZE(dove_ehci0_resources), +}; + +void __init dove_ehci0_init(void) +{ + platform_device_register(&dove_ehci0); +} + +/***************************************************************************** + * EHCI1 + ****************************************************************************/ +static struct resource dove_ehci1_resources[] = { + { + .start = DOVE_USB1_PHYS_BASE, + .end = DOVE_USB1_PHYS_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_DOVE_USB1, + .end = IRQ_DOVE_USB1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dove_ehci1 = { + .name = "orion-ehci", + .id = 1, + .dev = { + .dma_mask = &ehci_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &dove_ehci_data, + }, + .resource = dove_ehci1_resources, + .num_resources = ARRAY_SIZE(dove_ehci1_resources), +}; + +void __init dove_ehci1_init(void) +{ + platform_device_register(&dove_ehci1); +} + +/***************************************************************************** + * GE00 + ****************************************************************************/ +struct mv643xx_eth_shared_platform_data dove_ge00_shared_data = { + .t_clk = 0, + .dram = &dove_mbus_dram_info, +}; + +static struct resource dove_ge00_shared_resources[] = { + { + .name = "ge00 base", + .start = DOVE_GE00_PHYS_BASE + 0x2000, + .end = DOVE_GE00_PHYS_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device dove_ge00_shared = { + .name = MV643XX_ETH_SHARED_NAME, + .id = 0, + .dev = { + .platform_data = &dove_ge00_shared_data, + }, + .num_resources = 1, + .resource = dove_ge00_shared_resources, +}; + +static struct resource dove_ge00_resources[] = { + { + .name = "ge00 irq", + .start = IRQ_DOVE_GE00_SUM, + .end = IRQ_DOVE_GE00_SUM, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dove_ge00 = { + .name = MV643XX_ETH_NAME, + .id = 0, + .num_resources = 1, + .resource = dove_ge00_resources, + .dev = { + .coherent_dma_mask = 0xffffffff, + }, +}; + +void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data) +{ + eth_data->shared = &dove_ge00_shared; + dove_ge00.dev.platform_data = eth_data; + + platform_device_register(&dove_ge00_shared); + platform_device_register(&dove_ge00); +} + +/***************************************************************************** + * SoC RTC + ****************************************************************************/ +static struct resource dove_rtc_resource[] = { + { + .start = DOVE_RTC_PHYS_BASE, + .end = DOVE_RTC_PHYS_BASE + 32 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_DOVE_RTC, + .flags = IORESOURCE_IRQ, + } +}; + +void __init dove_rtc_init(void) +{ + platform_device_register_simple("rtc-mv", -1, dove_rtc_resource, 2); +} + +/***************************************************************************** + * SATA + ****************************************************************************/ +static struct resource dove_sata_resources[] = { + { + .name = "sata base", + .start = DOVE_SATA_PHYS_BASE, + .end = DOVE_SATA_PHYS_BASE + 0x5000 - 1, + .flags = IORESOURCE_MEM, + }, { + .name = "sata irq", + .start = IRQ_DOVE_SATA, + .end = IRQ_DOVE_SATA, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dove_sata = { + .name = "sata_mv", + .id = 0, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(dove_sata_resources), + .resource = dove_sata_resources, +}; + +void __init dove_sata_init(struct mv_sata_platform_data *sata_data) +{ + sata_data->dram = &dove_mbus_dram_info; + dove_sata.dev.platform_data = sata_data; + platform_device_register(&dove_sata); +} + +/***************************************************************************** + * UART0 + ****************************************************************************/ +static struct plat_serial8250_port dove_uart0_data[] = { + { + .mapbase = DOVE_UART0_PHYS_BASE, + .membase = (char *)DOVE_UART0_VIRT_BASE, + .irq = IRQ_DOVE_UART_0, + .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = 0, + }, { + }, +}; + +static struct resource dove_uart0_resources[] = { + { + .start = DOVE_UART0_PHYS_BASE, + .end = DOVE_UART0_PHYS_BASE + SZ_256 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_DOVE_UART_0, + .end = IRQ_DOVE_UART_0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dove_uart0 = { + .name = "serial8250", + .id = 0, + .dev = { + .platform_data = dove_uart0_data, + }, + .resource = dove_uart0_resources, + .num_resources = ARRAY_SIZE(dove_uart0_resources), +}; + +void __init dove_uart0_init(void) +{ + platform_device_register(&dove_uart0); +} + +/***************************************************************************** + * UART1 + ****************************************************************************/ +static struct plat_serial8250_port dove_uart1_data[] = { + { + .mapbase = DOVE_UART1_PHYS_BASE, + .membase = (char *)DOVE_UART1_VIRT_BASE, + .irq = IRQ_DOVE_UART_1, + .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = 0, + }, { + }, +}; + +static struct resource dove_uart1_resources[] = { + { + .start = DOVE_UART1_PHYS_BASE, + .end = DOVE_UART1_PHYS_BASE + SZ_256 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_DOVE_UART_1, + .end = IRQ_DOVE_UART_1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dove_uart1 = { + .name = "serial8250", + .id = 1, + .dev = { + .platform_data = dove_uart1_data, + }, + .resource = dove_uart1_resources, + .num_resources = ARRAY_SIZE(dove_uart1_resources), +}; + +void __init dove_uart1_init(void) +{ + platform_device_register(&dove_uart1); +} + +/***************************************************************************** + * UART2 + ****************************************************************************/ +static struct plat_serial8250_port dove_uart2_data[] = { + { + .mapbase = DOVE_UART2_PHYS_BASE, + .membase = (char *)DOVE_UART2_VIRT_BASE, + .irq = IRQ_DOVE_UART_2, + .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = 0, + }, { + }, +}; + +static struct resource dove_uart2_resources[] = { + { + .start = DOVE_UART2_PHYS_BASE, + .end = DOVE_UART2_PHYS_BASE + SZ_256 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_DOVE_UART_2, + .end = IRQ_DOVE_UART_2, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dove_uart2 = { + .name = "serial8250", + .id = 2, + .dev = { + .platform_data = dove_uart2_data, + }, + .resource = dove_uart2_resources, + .num_resources = ARRAY_SIZE(dove_uart2_resources), +}; + +void __init dove_uart2_init(void) +{ + platform_device_register(&dove_uart2); +} + +/***************************************************************************** + * UART3 + ****************************************************************************/ +static struct plat_serial8250_port dove_uart3_data[] = { + { + .mapbase = DOVE_UART3_PHYS_BASE, + .membase = (char *)DOVE_UART3_VIRT_BASE, + .irq = IRQ_DOVE_UART_3, + .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = 0, + }, { + }, +}; + +static struct resource dove_uart3_resources[] = { + { + .start = DOVE_UART3_PHYS_BASE, + .end = DOVE_UART3_PHYS_BASE + SZ_256 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_DOVE_UART_3, + .end = IRQ_DOVE_UART_3, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dove_uart3 = { + .name = "serial8250", + .id = 3, + .dev = { + .platform_data = dove_uart3_data, + }, + .resource = dove_uart3_resources, + .num_resources = ARRAY_SIZE(dove_uart3_resources), +}; + +void __init dove_uart3_init(void) +{ + platform_device_register(&dove_uart3); +} + +/***************************************************************************** + * SPI0 + ****************************************************************************/ +static struct orion_spi_info dove_spi0_data = { + .tclk = 0, +}; + +static struct resource dove_spi0_resources[] = { + { + .start = DOVE_SPI0_PHYS_BASE, + .end = DOVE_SPI0_PHYS_BASE + SZ_512 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_DOVE_SPI0, + .end = IRQ_DOVE_SPI0, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dove_spi0 = { + .name = "orion_spi", + .id = 0, + .resource = dove_spi0_resources, + .dev = { + .platform_data = &dove_spi0_data, + }, + .num_resources = ARRAY_SIZE(dove_spi0_resources), +}; + +void __init dove_spi0_init(void) +{ + platform_device_register(&dove_spi0); +} + +/***************************************************************************** + * SPI1 + ****************************************************************************/ +static struct orion_spi_info dove_spi1_data = { + .tclk = 0, +}; + +static struct resource dove_spi1_resources[] = { + { + .start = DOVE_SPI1_PHYS_BASE, + .end = DOVE_SPI1_PHYS_BASE + SZ_512 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_DOVE_SPI1, + .end = IRQ_DOVE_SPI1, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dove_spi1 = { + .name = "orion_spi", + .id = 1, + .resource = dove_spi1_resources, + .dev = { + .platform_data = &dove_spi1_data, + }, + .num_resources = ARRAY_SIZE(dove_spi1_resources), +}; + +void __init dove_spi1_init(void) +{ + platform_device_register(&dove_spi1); +} + +/***************************************************************************** + * I2C + ****************************************************************************/ +static struct mv64xxx_i2c_pdata dove_i2c_data = { + .freq_m = 10, /* assumes 166 MHz TCLK gets 94.3kHz */ + .freq_n = 3, + .timeout = 1000, /* Default timeout of 1 second */ +}; + +static struct resource dove_i2c_resources[] = { + { + .name = "i2c base", + .start = DOVE_I2C_PHYS_BASE, + .end = DOVE_I2C_PHYS_BASE + 0x20 - 1, + .flags = IORESOURCE_MEM, + }, { + .name = "i2c irq", + .start = IRQ_DOVE_I2C, + .end = IRQ_DOVE_I2C, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device dove_i2c = { + .name = MV64XXX_I2C_CTLR_NAME, + .id = 0, + .num_resources = ARRAY_SIZE(dove_i2c_resources), + .resource = dove_i2c_resources, + .dev = { + .platform_data = &dove_i2c_data, + }, +}; + +void __init dove_i2c_init(void) +{ + platform_device_register(&dove_i2c); +} + +/***************************************************************************** + * Time handling + ****************************************************************************/ +static int get_tclk(void) +{ + /* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */ + return 166666667; +} + +static void dove_timer_init(void) +{ + orion_time_init(IRQ_DOVE_BRIDGE, get_tclk()); +} + +struct sys_timer dove_timer = { + .init = dove_timer_init, +}; + +/***************************************************************************** + * XOR + ****************************************************************************/ +static struct mv_xor_platform_shared_data dove_xor_shared_data = { + .dram = &dove_mbus_dram_info, +}; + +/***************************************************************************** + * XOR 0 + ****************************************************************************/ +static u64 dove_xor0_dmamask = DMA_BIT_MASK(32); + +static struct resource dove_xor0_shared_resources[] = { + { + .name = "xor 0 low", + .start = DOVE_XOR0_PHYS_BASE, + .end = DOVE_XOR0_PHYS_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, { + .name = "xor 0 high", + .start = DOVE_XOR0_HIGH_PHYS_BASE, + .end = DOVE_XOR0_HIGH_PHYS_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device dove_xor0_shared = { + .name = MV_XOR_SHARED_NAME, + .id = 0, + .dev = { + .platform_data = &dove_xor_shared_data, + }, + .num_resources = ARRAY_SIZE(dove_xor0_shared_resources), + .resource = dove_xor0_shared_resources, +}; + +static struct resource dove_xor00_resources[] = { + [0] = { + .start = IRQ_DOVE_XOR_00, + .end = IRQ_DOVE_XOR_00, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct mv_xor_platform_data dove_xor00_data = { + .shared = &dove_xor0_shared, + .hw_id = 0, + .pool_size = PAGE_SIZE, +}; + +static struct platform_device dove_xor00_channel = { + .name = MV_XOR_NAME, + .id = 0, + .num_resources = ARRAY_SIZE(dove_xor00_resources), + .resource = dove_xor00_resources, + .dev = { + .dma_mask = &dove_xor0_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(64), + .platform_data = (void *)&dove_xor00_data, + }, +}; + +static struct resource dove_xor01_resources[] = { + [0] = { + .start = IRQ_DOVE_XOR_01, + .end = IRQ_DOVE_XOR_01, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct mv_xor_platform_data dove_xor01_data = { + .shared = &dove_xor0_shared, + .hw_id = 1, + .pool_size = PAGE_SIZE, +}; + +static struct platform_device dove_xor01_channel = { + .name = MV_XOR_NAME, + .id = 1, + .num_resources = ARRAY_SIZE(dove_xor01_resources), + .resource = dove_xor01_resources, + .dev = { + .dma_mask = &dove_xor0_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(64), + .platform_data = (void *)&dove_xor01_data, + }, +}; + +void __init dove_xor0_init(void) +{ + platform_device_register(&dove_xor0_shared); + + /* + * two engines can't do memset simultaneously, this limitation + * satisfied by removing memset support from one of the engines. + */ + dma_cap_set(DMA_MEMCPY, dove_xor00_data.cap_mask); + dma_cap_set(DMA_XOR, dove_xor00_data.cap_mask); + platform_device_register(&dove_xor00_channel); + + dma_cap_set(DMA_MEMCPY, dove_xor01_data.cap_mask); + dma_cap_set(DMA_MEMSET, dove_xor01_data.cap_mask); + dma_cap_set(DMA_XOR, dove_xor01_data.cap_mask); + platform_device_register(&dove_xor01_channel); +} + +/***************************************************************************** + * XOR 1 + ****************************************************************************/ +static u64 dove_xor1_dmamask = DMA_BIT_MASK(32); + +static struct resource dove_xor1_shared_resources[] = { + { + .name = "xor 0 low", + .start = DOVE_XOR1_PHYS_BASE, + .end = DOVE_XOR1_PHYS_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, { + .name = "xor 0 high", + .start = DOVE_XOR1_HIGH_PHYS_BASE, + .end = DOVE_XOR1_HIGH_PHYS_BASE + 0xff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device dove_xor1_shared = { + .name = MV_XOR_SHARED_NAME, + .id = 1, + .dev = { + .platform_data = &dove_xor_shared_data, + }, + .num_resources = ARRAY_SIZE(dove_xor1_shared_resources), + .resource = dove_xor1_shared_resources, +}; + +static struct resource dove_xor10_resources[] = { + [0] = { + .start = IRQ_DOVE_XOR_10, + .end = IRQ_DOVE_XOR_10, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct mv_xor_platform_data dove_xor10_data = { + .shared = &dove_xor1_shared, + .hw_id = 0, + .pool_size = PAGE_SIZE, +}; + +static struct platform_device dove_xor10_channel = { + .name = MV_XOR_NAME, + .id = 2, + .num_resources = ARRAY_SIZE(dove_xor10_resources), + .resource = dove_xor10_resources, + .dev = { + .dma_mask = &dove_xor1_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(64), + .platform_data = (void *)&dove_xor10_data, + }, +}; + +static struct resource dove_xor11_resources[] = { + [0] = { + .start = IRQ_DOVE_XOR_11, + .end = IRQ_DOVE_XOR_11, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct mv_xor_platform_data dove_xor11_data = { + .shared = &dove_xor1_shared, + .hw_id = 1, + .pool_size = PAGE_SIZE, +}; + +static struct platform_device dove_xor11_channel = { + .name = MV_XOR_NAME, + .id = 3, + .num_resources = ARRAY_SIZE(dove_xor11_resources), + .resource = dove_xor11_resources, + .dev = { + .dma_mask = &dove_xor1_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(64), + .platform_data = (void *)&dove_xor11_data, + }, +}; + +void __init dove_xor1_init(void) +{ + platform_device_register(&dove_xor1_shared); + + /* + * two engines can't do memset simultaneously, this limitation + * satisfied by removing memset support from one of the engines. + */ + dma_cap_set(DMA_MEMCPY, dove_xor10_data.cap_mask); + dma_cap_set(DMA_XOR, dove_xor10_data.cap_mask); + platform_device_register(&dove_xor10_channel); + + dma_cap_set(DMA_MEMCPY, dove_xor11_data.cap_mask); + dma_cap_set(DMA_MEMSET, dove_xor11_data.cap_mask); + dma_cap_set(DMA_XOR, dove_xor11_data.cap_mask); + platform_device_register(&dove_xor11_channel); +} + +void __init dove_init(void) +{ + int tclk; + + tclk = get_tclk(); + + printk(KERN_INFO "Dove 88AP510 SoC, "); + printk(KERN_INFO "TCLK = %dMHz\n", (tclk + 499999) / 1000000); + + dove_setup_cpu_mbus(); + + dove_ge00_shared_data.t_clk = tclk; + dove_uart0_data[0].uartclk = tclk; + dove_uart1_data[0].uartclk = tclk; + dove_uart2_data[0].uartclk = tclk; + dove_uart3_data[0].uartclk = tclk; + dove_spi0_data.tclk = tclk; + dove_spi1_data.tclk = tclk; + + /* internal devices that every board has */ + dove_rtc_init(); + dove_xor0_init(); + dove_xor1_init(); +} diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h new file mode 100644 index 000000000000..b29e8937de4f --- /dev/null +++ b/arch/arm/mach-dove/common.h @@ -0,0 +1,40 @@ +/* + * arch/arm/mach-dove/common.h + * + * Core functions for Marvell Dove 88AP510 System On Chip + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ARCH_DOVE_COMMON_H +#define __ARCH_DOVE_COMMON_H + +struct mv643xx_eth_platform_data; +struct mv_sata_platform_data; + +extern struct sys_timer dove_timer; +extern struct mbus_dram_target_info dove_mbus_dram_info; + +/* + * Basic Dove init functions used early by machine-setup. + */ +void dove_map_io(void); +void dove_init(void); +void dove_init_irq(void); +void dove_setup_cpu_mbus(void); +void dove_ge00_init(struct mv643xx_eth_platfo |