diff options
author | Olof Johansson <olof@lixom.net> | 2020-01-16 12:48:50 -0800 |
---|---|---|
committer | Olof Johansson <olof@lixom.net> | 2020-01-16 12:48:52 -0800 |
commit | 7d6292ab11199ef596cbe6c87180e49510c8b7c7 (patch) | |
tree | d1fa6b165c835a49a131677a1944fb71b5340bf6 /arch/arm/boot | |
parent | 87f846c773ea43d23be7d478201cc83a3d70fb5f (diff) | |
parent | ac904843087bed19e702c507ab0250abf56d2625 (diff) |
Merge tag 'sunxi-dt-for-5.6-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt
This is our usual set of DT patches for the Allwinner SoCs.
It's fairly big this time, but the highlights are:
- Enable cpufreq and CPU thermal throttling on the A64
- CLK_CPUX macro usage removed (changed from first pull request)
- CSI0 support on the R40
- CSI1 support on the A10 and A20
- SPI support on the R40
- PMU support on the H3, H5, H6 and R40
- MIPI-DSI support on the A64
- PWM support on the H6
- Thermal sensor on the A64, A83t, H3, H5, H6 and R40
- More DT schemas fixes and conversions
- New boards: LibreComputer ALL-H5-CC H5, LibreComputer ALL-H3-IT H5,
Pine64 H64 Model B, Neutis N5H3
* tag 'sunxi-dt-for-5.6-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (52 commits)
arm64: dts: allwinner: a64: enable DVFS
arm64: dts: allwinner: a64: add dtsi with CPU operating points
arm64: dts: allwinner: a64: add cooling maps and thermal tripping points
arm64: dts: allwinner: a64: add CPU clock to CPU0-3 nodes
arm64: dts: allwinner: sun50i-a64: Use macros for newly exported clocks
ARM: dts: sunxi: Use macros for references to CCU clocks
arm64: dts: allwinner: h5: Add Libre Computer ALL-H5-CC H5 board
ARM: dts: sun8i: R40: Add SPI controllers nodes and pinmuxes
arm64: dts: allwinner: a64: pinebook: Fix lid wakeup
ARM: dts: sun8i: r40: Add device node for CSI0
ARM: dts: sun7i: Add CSI1 controller and pinmux options
ARM: dts: sun4i: Add CSI1 controller and pinmux options
ARM: dts: sunxi: Add missing LVDS resets and clocks
ARM: dts: sun8i: r40: Use tcon top clock index macros
ARM: dts: sun8i: R40: Add PMU node
ARM: dts: sun8i: R40: Upgrade GICC reg size to 8K
arm64: dts: allwinner: h6: Add thermal sensor and thermal zones
ARM: dts: sunxi: Add Libre Computer ALL-H3-IT H5 board
arm64: dts: allwinner: a64: Add MIPI DSI pipeline
arm64: dts: allwinner: a64: Add thermal sensors and thermal zones
...
Link: https://lore.kernel.org/r/20200113095555.GA29848@wens.csie.org
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/boot')
-rw-r--r-- | arch/arm/boot/dts/Makefile | 1 | ||||
-rw-r--r-- | arch/arm/boot/dts/sun4i-a10.dtsi | 35 | ||||
-rw-r--r-- | arch/arm/boot/dts/sun5i.dtsi | 3 | ||||
-rw-r--r-- | arch/arm/boot/dts/sun6i-a31.dtsi | 25 | ||||
-rw-r--r-- | arch/arm/boot/dts/sun7i-a20.dtsi | 36 | ||||
-rw-r--r-- | arch/arm/boot/dts/sun8i-a23-a33.dtsi | 13 | ||||
-rw-r--r-- | arch/arm/boot/dts/sun8i-a83t.dtsi | 42 | ||||
-rw-r--r-- | arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 1 | ||||
-rw-r--r-- | arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3-devboard.dts | 72 | ||||
-rw-r--r-- | arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3.dtsi | 11 | ||||
-rw-r--r-- | arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts | 3 | ||||
-rw-r--r-- | arch/arm/boot/dts/sun8i-h3.dtsi | 35 | ||||
-rw-r--r-- | arch/arm/boot/dts/sun8i-r40.dtsi | 172 | ||||
-rw-r--r-- | arch/arm/boot/dts/sun8i-v3s.dtsi | 2 | ||||
-rw-r--r-- | arch/arm/boot/dts/sun9i-a80.dtsi | 42 | ||||
-rw-r--r-- | arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi | 170 | ||||
-rw-r--r-- | arch/arm/boot/dts/sunxi-h3-h5.dtsi | 13 | ||||
-rw-r--r-- | arch/arm/boot/dts/sunxi-libretech-all-h3-it.dtsi | 180 |
18 files changed, 802 insertions, 54 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bf2ba9ccacc2..6bf729efddd3 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1139,6 +1139,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-h3-orangepi-plus2e.dtb \ sun8i-h3-orangepi-zero-plus2.dtb \ sun8i-h3-rervision-dvk.dtb \ + sun8i-h3-emlid-neutis-n5h3-devboard.dtb \ sun8i-r16-bananapi-m2m.dtb \ sun8i-r16-nintendo-nes-classic.dtb \ sun8i-r16-nintendo-super-nes-classic.dtb \ diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 4c268b70b735..bf531efc0610 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -624,6 +624,16 @@ status = "disabled"; }; + csi1: csi@1c1d000 { + compatible = "allwinner,sun4i-a10-csi1"; + reg = <0x01c1d000 0x1000>; + interrupts = <43>; + clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>; + clock-names = "bus", "ram"; + resets = <&ccu RST_CSI1>; + status = "disabled"; + }; + spi3: spi@1c1f000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c1f000 0x1000>; @@ -670,6 +680,31 @@ function = "can"; }; + /omit-if-no-ref/ + csi1_8bits_pg_pins: csi1-8bits-pg-pins { + pins = "PG0", "PG2", "PG3", "PG4", "PG5", + "PG6", "PG7", "PG8", "PG9", "PG10", + "PG11"; + function = "csi1"; + }; + + /omit-if-no-ref/ + csi1_24bits_ph_pins: csi1-24bits-ph-pins { + pins = "PH0", "PH1", "PH2", "PH3", "PH4", + "PH5", "PH6", "PH7", "PH8", "PH9", + "PH10", "PH11", "PH12", "PH13", "PH14", + "PH15", "PH16", "PH17", "PH18", "PH19", + "PH20", "PH21", "PH22", "PH23", "PH24", + "PH25", "PH26", "PH27"; + function = "csi1"; + }; + + /omit-if-no-ref/ + csi1_clk_pg_pin: csi1-clk-pg-pin { + pins = "PG1"; + function = "csi1"; + }; + emac_pins: emac0-pins { pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index 6befa236ba99..0b526e6e5a95 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -185,7 +185,7 @@ mbus: dram-controller@1c01000 { compatible = "allwinner,sun5i-a13-mbus"; reg = <0x01c01000 0x1000>; - clocks = <&ccu 99>; + clocks = <&ccu CLK_MBUS>; dma-ranges = <0x00000000 0x40000000 0x20000000>; #interconnect-cells = <1>; }; @@ -275,6 +275,7 @@ compatible = "allwinner,sun5i-a13-tcon"; reg = <0x01c0c000 0x1000>; interrupts = <44>; + dmas = <&dma SUN4I_DMA_DEDICATED 14>; resets = <&ccu RST_LCD>; reset-names = "lcd"; clocks = <&ccu CLK_AHB_LCD>, diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 2cf34ae1c17b..7762fbd9a133 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -285,14 +285,19 @@ compatible = "allwinner,sun6i-a31-tcon"; reg = <0x01c0c000 0x1000>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - resets = <&ccu RST_AHB1_LCD0>; - reset-names = "lcd"; + dmas = <&dma 11>; + resets = <&ccu RST_AHB1_LCD0>, + <&ccu RST_AHB1_LVDS>; + reset-names = "lcd", + "lvds"; clocks = <&ccu CLK_AHB1_LCD0>, <&ccu CLK_LCD0_CH0>, - <&ccu CLK_LCD0_CH1>; + <&ccu CLK_LCD0_CH1>, + <&ccu 15>; clock-names = "ahb", "tcon-ch0", - "tcon-ch1"; + "tcon-ch1", + "lvds-alt"; clock-output-names = "tcon0-pixel-clock"; #clock-cells = <0>; @@ -334,14 +339,18 @@ compatible = "allwinner,sun6i-a31-tcon"; reg = <0x01c0d000 0x1000>; interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; - resets = <&ccu RST_AHB1_LCD1>; - reset-names = "lcd"; + dmas = <&dma 12>; + resets = <&ccu RST_AHB1_LCD1>, + <&ccu RST_AHB1_LVDS>; + reset-names = "lcd", "lvds"; clocks = <&ccu CLK_AHB1_LCD1>, <&ccu CLK_LCD1_CH0>, - <&ccu CLK_LCD1_CH1>; + <&ccu CLK_LCD1_CH1>, + <&ccu 15>; clock-names = "ahb", "tcon-ch0", - "tcon-ch1"; + "tcon-ch1", + "lvds-alt"; clock-output-names = "tcon1-pixel-clock"; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 8aebefd6accf..92b5be97085d 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -729,6 +729,17 @@ status = "disabled"; }; + csi1: csi@1c1d000 { + compatible = "allwinner,sun7i-a20-csi1", + "allwinner,sun4i-a10-csi1"; + reg = <0x01c1d000 0x1000>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>; + clock-names = "bus", "ram"; + resets = <&ccu RST_CSI1>; + status = "disabled"; + }; + spi3: spi@1c1f000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c1f000 0x1000>; @@ -803,6 +814,31 @@ }; /omit-if-no-ref/ + csi1_8bits_pg_pins: csi1-8bits-pg-pins { + pins = "PG0", "PG2", "PG3", "PG4", "PG5", + "PG6", "PG7", "PG8", "PG9", "PG10", + "PG11"; + function = "csi1"; + }; + + /omit-if-no-ref/ + csi1_24bits_ph_pins: csi1-24bits-ph-pins { + pins = "PH0", "PH1", "PH2", "PH3", "PH4", + "PH5", "PH6", "PH7", "PH8", "PH9", + "PH10", "PH11", "PH12", "PH13", "PH14", + "PH15", "PH16", "PH17", "PH18", "PH19", + "PH20", "PH21", "PH22", "PH23", "PH24", + "PH25", "PH26", "PH27"; + function = "csi1"; + }; + + /omit-if-no-ref/ + csi1_clk_pg_pin: csi1-clk-pg-pin { + pins = "PG1"; + function = "csi1"; + }; + + /omit-if-no-ref/ emac_pa_pins: emac-pa-pins { pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index f292f96ab39b..48487f6d4ab9 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -182,14 +182,19 @@ /* compatible gets set in SoC specific dtsi file */ reg = <0x01c0c000 0x1000>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma 12>; clocks = <&ccu CLK_BUS_LCD>, - <&ccu CLK_LCD_CH0>; + <&ccu CLK_LCD_CH0>, + <&ccu 13>; clock-names = "ahb", - "tcon-ch0"; + "tcon-ch0", + "lvds-alt"; clock-output-names = "tcon-pixel-clock"; #clock-cells = <0>; - resets = <&ccu RST_BUS_LCD>; - reset-names = "lcd"; + resets = <&ccu RST_BUS_LCD>, + <&ccu RST_BUS_LVDS>; + reset-names = "lcd", + "lvds"; status = "disabled"; ports { diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 53c38deb8a08..74ac7ee9383c 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -50,6 +50,7 @@ #include <dt-bindings/reset/sun8i-a83t-ccu.h> #include <dt-bindings/reset/sun8i-de2.h> #include <dt-bindings/reset/sun8i-r-ccu.h> +#include <dt-bindings/thermal/thermal.h> / { interrupt-parent = <&gic>; @@ -581,6 +582,12 @@ sid: eeprom@1c14000 { compatible = "allwinner,sun8i-a83t-sid"; reg = <0x1c14000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + + ths_calibration: thermal-sensor-calibration@34 { + reg = <0x34 8>; + }; }; crypto: crypto@1c15000 { @@ -999,9 +1006,9 @@ reg = <0x01c30000 0x104>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; - resets = <&ccu 13>; + resets = <&ccu CLK_BUS_EMAC>; reset-names = "stmmaceth"; - clocks = <&ccu 27>; + clocks = <&ccu RST_BUS_EMAC>; clock-names = "stmmaceth"; status = "disabled"; @@ -1095,7 +1102,7 @@ compatible = "allwinner,sun8i-a83t-r-ccu"; reg = <0x01f01400 0x400>; clocks = <&osc24M>, <&osc16Md512>, <&osc16M>, - <&ccu 6>; + <&ccu CLK_PLL_PERIPH>; clock-names = "hosc", "losc", "iosc", "pll-periph"; #clock-cells = <1>; #reset-cells = <1>; @@ -1165,5 +1172,34 @@ #address-cells = <1>; #size-cells = <0>; }; + + ths: thermal-sensor@1f04000 { + compatible = "allwinner,sun8i-a83t-ths"; + reg = <0x01f04000 0x100>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <1>; + }; + }; + + thermal-zones { + cpu0_thermal: cpu0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 0>; + }; + + cpu1_thermal: cpu1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 1>; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 2>; + }; }; }; diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts index ac9e26b1d906..45a24441ff18 100644 --- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts +++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts @@ -143,6 +143,7 @@ }; &ir { + linux,rc-map-name = "rc-tanix-tx3mini"; pinctrl-names = "default"; pinctrl-0 = <&r_ir_rx_pin>; status = "okay"; diff --git a/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3-devboard.dts b/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3-devboard.dts new file mode 100644 index 000000000000..02fbe00cde97 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3-devboard.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * DTS for Emlid Neutis N5 Dev board. + * + * Copyright (C) 2019 Georgii Staroselskii <georgiii.staroselskii@emlid.com> + */ + +/dts-v1/; + +#include "sun8i-h3-emlid-neutis-n5h3.dtsi" + +/ { + model = "Emlid Neutis N5H3 Developer board"; + compatible = "emlid,neutis-n5h3-devboard", + "emlid,neutis-n5h3", + "allwinner,sun8i-h3"; + + vdd_cpux: gpio-regulator { + compatible = "regulator-gpio"; + regulator-name = "vdd-cpux"; + regulator-type = "voltage"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <50>; /* 4ms */ + gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ + gpios-states = <0x1>; + states = <1100000 0x0>, <1300000 0x1>; + }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + +}; + +&cpu0 { + cpu-supply = <&vdd_cpux>; +}; + +&codec { + status = "okay"; +}; + +&emac { + phy-handle = <&int_mii_phy>; + phy-mode = "mii"; + allwinner,leds-active-low; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3.dtsi b/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3.dtsi new file mode 100644 index 000000000000..eedd5da5dc2f --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h3-emlid-neutis-n5h3.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * DTSI for Emlid Neutis N5 SoM. + * + * Copyright (C) 2019 Georgii Staroselskii <georgii.staroselskii@emlid.com> + */ + +/dts-v1/; + +#include "sun8i-h3.dtsi" +#include <arm/sunxi-h3-h5-emlid-neutis.dtsi> diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts index c73f59900975..6b149271ef13 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts @@ -60,8 +60,7 @@ enable-gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ gpios-states = <0x1>; - states = <1100000 0x0 - 1300000 0x1>; + states = <1100000 0>, <1300000 1>; }; reg_vcc_dram: vcc-dram { diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index fe773c72a69b..20217e2ca4d3 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -80,7 +80,7 @@ #cooling-cells = <2>; }; - cpu@1 { + cpu1: cpu@1 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; @@ -90,7 +90,7 @@ #cooling-cells = <2>; }; - cpu@2 { + cpu2: cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <2>; @@ -100,7 +100,7 @@ #cooling-cells = <2>; }; - cpu@3 { + cpu3: cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <3>; @@ -111,6 +111,15 @@ }; }; + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + timer { compatible = "arm,armv7-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, @@ -199,6 +208,26 @@ assigned-clocks = <&ccu CLK_GPU>; assigned-clock-rates = <384000000>; }; + + ths: thermal-sensor@1c25000 { + compatible = "allwinner,sun8i-h3-ths"; + reg = <0x01c25000 0x400>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + resets = <&ccu RST_BUS_THS>; + clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; + clock-names = "bus", "mod"; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <0>; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 0>; + }; }; }; diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index 421dfbbfd7ee..8f09a24b36ec 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -44,6 +44,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/sun8i-de2.h> #include <dt-bindings/clock/sun8i-r40-ccu.h> +#include <dt-bindings/clock/sun8i-tcon-top.h> #include <dt-bindings/reset/sun8i-r40-ccu.h> #include <dt-bindings/reset/sun8i-de2.h> @@ -78,25 +79,25 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; }; - cpu@1 { + cpu1: cpu@1 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; }; - cpu@2 { + cpu2: cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <2>; }; - cpu@3 { + cpu3: cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <3>; @@ -180,6 +181,20 @@ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; }; + csi0: csi@1c09000 { + compatible = "allwinner,sun8i-r40-csi0", + "allwinner,sun7i-a20-csi0"; + reg = <0x01c09000 0x1000>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_CSI0>, <&ccu CLK_CSI_SCLK>, + <&ccu CLK_DRAM_CSI0>; + clock-names = "bus", "isp", "ram"; + resets = <&ccu RST_BUS_CSI0>; + interconnects = <&mbus 5>; + interconnect-names = "dma-mem"; + status = "disabled"; + }; + mmc0: mmc@1c0f000 { compatible = "allwinner,sun8i-r40-mmc", "allwinner,sun50i-a64-mmc"; @@ -355,6 +370,20 @@ function = "clk_out_a"; }; + /omit-if-no-ref/ + csi0_8bits_pins: csi0-8bits-pins { + pins = "PE0", "PE2", "PE3", "PE4", "PE5", + "PE6", "PE7", "PE8", "PE9", "PE10", + "PE11"; + function = "csi0"; + }; + + /omit-if-no-ref/ + csi0_mclk_pin: csi0-mclk-pin { + pins = "PE1"; + function = "csi0"; + }; + gmac_rgmii_pins: gmac-rgmii-pins { pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", @@ -373,6 +402,26 @@ function = "i2c0"; }; + i2c1_pins: i2c1-pins { + pins = "PB18", "PB19"; + function = "i2c1"; + }; + + i2c2_pins: i2c2-pins { + pins = "PB20", "PB21"; + function = "i2c2"; + }; + + i2c3_pins: i2c3-pins { + pins = "PI0", "PI1"; + function = "i2c3"; + }; + + i2c4_pins: i2c4-pins { + pins = "PI2", "PI3"; + function = "i2c4"; + }; + mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; @@ -398,6 +447,36 @@ bias-pull-up; }; + /omit-if-no-ref/ + spi0_pc_pins: spi0-pc-pins { + pins = "PC0", "PC1", "PC2"; + function = "spi0"; + }; + + /omit-if-no-ref/ + spi0_cs0_pc_pin: spi0-cs0-pc-pin { + pins = "PC23"; + function = "spi0"; + }; + + /omit-if-no-ref/ + spi1_pi_pins: spi1-pi-pins { + pins = "PI17", "PI18", "PI19"; + function = "spi1"; + }; + + /omit-if-no-ref/ + spi1_cs0_pi_pin: spi1-cs0-pi-pin { + pins = "PI16"; + function = "spi1"; + }; + + /omit-if-no-ref/ + spi1_cs1_pi_pin: spi1-cs1-pi-pin { + pins = "PI15"; + function = "spi1"; + }; + uart0_pb_pins: uart0-pb-pins { pins = "PB22", "PB23"; function = "uart0"; @@ -528,6 +607,8 @@ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C1>; resets = <&ccu RST_BUS_I2C1>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -539,6 +620,8 @@ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C2>; resets = <&ccu RST_BUS_I2C2>; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -550,6 +633,8 @@ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C3>; resets = <&ccu RST_BUS_I2C3>; + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -561,6 +646,60 @@ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_I2C4>; resets = <&ccu RST_BUS_I2C4>; + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "default"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi0: spi@1c05000 { + compatible = "allwinner,sun8i-r40-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c05000 0x1000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@1c06000 { + compatible = "allwinner,sun8i-r40-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c06000 0x1000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi2: spi@1c07000 { + compatible = "allwinner,sun8i-r40-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c07000 0x1000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi3: spi@1c0f000 { + compatible = "allwinner,sun8i-r40-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c0f000 0x1000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI3>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -596,6 +735,14 @@ }; }; + mbus: dram-controller@1c62000 { + compatible = "allwinner,sun8i-r40-mbus"; + reg = <0x01c62000 0x1000>; + clocks = <&ccu 155>; + dma-ranges = <0x00000000 0x40000000 0x80000000>; + #interconnect-cells = <1>; + }; + tcon_top: tcon-top@1c70000 { compatible = "allwinner,sun8i-r40-tcon-top"; reg = <0x01c70000 0x1000>; @@ -718,7 +865,7 @@ compatible = "allwinner,sun8i-r40-tcon-tv"; reg = <0x01c73000 0x1000>; interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>; + clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top CLK_TCON_TOP_TV0>; clock-names = "ahb", "tcon-ch1"; resets = <&ccu RST_BUS_TCON_TV0>; reset-names = "lcd"; @@ -761,7 +908,7 @@ compatible = "allwinner,sun8i-r40-tcon-tv"; reg = <0x01c74000 0x1000>; interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top 1>; + clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top CLK_TCON_TOP_TV1>; clock-names = "ahb", "tcon-ch1"; resets = <&ccu RST_BUS_TCON_TV1>; reset-names = "lcd"; @@ -803,7 +950,7 @@ gic: interrupt-controller@1c81000 { compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>, - <0x01c82000 0x1000>, + <0x01c82000 0x2000>, <0x01c84000 0x2000>, <0x01c86000 0x2000>; interrupt-controller; @@ -848,7 +995,7 @@ compatible = "allwinner,sun8i-r40-hdmi-phy"; reg = <0x01ef0000 0x10000>; clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>, - <&ccu 7>, <&ccu 16>; + <&ccu CLK_PLL_VIDEO0>, <&ccu CLK_PLL_VIDEO1>; clock-names = "bus", "mod", "pll-0", "pll-1"; resets = <&ccu RST_BUS_HDMI0>; reset-names = "phy"; @@ -856,6 +1003,15 @@ }; }; + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + timer { compatible = "arm,armv7-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 23ba56df38f7..81ea50838cd5 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -123,8 +123,6 @@ clock-names = "bus", "mod"; resets = <&display_clocks 0>; - assigned-clocks = <&display_clocks 6>; - assigned-clock-rates = <150000000>; ports { #address-cells = <1>; diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index 1d900f591d5f..ce4fa6706d06 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -387,16 +387,16 @@ usbphy2: phy@a01800 { compatible = "allwinner,sun9i-a80-usb-phy"; reg = <0x00a01800 0x4>; - clocks = <&usb_clocks CLK_USB1_HSIC>, + clocks = <&usb_clocks CLK_USB1_PHY>, <&usb_clocks CLK_USB_HSIC>, - <&usb_clocks CLK_USB1_PHY>; - clock-names = "hsic_480M", + <&usb_clocks CLK_USB1_HSIC>; + clock-names = "phy", "hsic_12M", - "phy"; - resets = <&usb_clocks RST_USB1_HSIC>, - <&usb_clocks RST_USB1_PHY>; - reset-names = "hsic", - "phy"; + "hsic_480M"; + resets = <&usb_clocks RST_USB1_PHY>, + <&usb_clocks RST_USB1_HSIC>; + reset-names = "phy", + "hsic"; status = "disabled"; #phy-cells = <0>; /* usb1 is always used with HSIC */ @@ -429,16 +429,16 @@ usbphy3: phy@a02800 { compatible = "allwinner,sun9i-a80-usb-phy"; reg = <0x00a02800 0x4>; - clocks = <&usb_clocks CLK_USB2_HSIC>, + clocks = <&usb_clocks CLK_USB2_PHY>, <&usb_clocks CLK_USB_HSIC>, - <&usb_clocks CLK_USB2_PHY>; - clock-names = "hsic_480M", + <&usb_clocks CLK_USB2_HSIC>; + clock-names = "phy", "hsic_12M", - "phy"; - resets = <&usb_clocks RST_USB2_HSIC>, - <&usb_clocks RST_USB2_PHY>; - reset-names = "hsic", - "phy"; + "hsic_480M"; + resets = <&usb_clocks RST_USB2_PHY>, + <&usb_clocks RST_USB2_HSIC>; + reset-names = "phy", + "hsic"; status = "disabled"; #phy-cells = <0>; }; @@ -530,9 +530,7 @@ compatible = "allwinner,sun9i-a80-mmc-config-clk"; reg = <0x01c13000 0x10>; clocks = <&ccu CLK_BUS_MMC>; - clock-names = "ahb"; resets = <&ccu RST_BUS_MMC>; - reset-names = "ahb"; #clock-cells = <1>; #reset-cells = <1>; clock-output-names = "mmc0_config", "mmc1_config", @@ -880,8 +878,12 @@ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>; clock-names = "ahb", "tcon-ch0"; - resets = <&ccu RST_BUS_LCD0>, <&ccu RST_BUS_EDP>; - reset-names = "lcd", "edp"; + resets = <&ccu RST_BUS_LCD0>, + <&ccu RST_BUS_EDP>, + <&ccu RST_BUS_LVDS>; + reset-names = "lcd", + "edp", + "lvds"; clock-output-names = "tcon0-pixel-clock"; #clock-cells = <0>; diff --git a/arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi b/arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi new file mode 100644 index 000000000000..fc67e30fe212 --- /dev/null +++ b/arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * DTSI for Emlid N |