diff options
author | Jernej Skrabec <jernej.skrabec@siol.net> | 2020-01-25 00:20:09 +0100 |
---|---|---|
committer | Chen-Yu Tsai <wens@csie.org> | 2020-03-12 00:24:29 +0800 |
commit | da180322582bd9db07f29e6d4a2d170afde0703f (patch) | |
tree | 3796c1c8458572d691f5b8ec3b952508c0fbc6e2 /arch/arm/boot/dts/sunxi-h3-h5.dtsi | |
parent | 2345b744f4f911713dcada64ea16a614f5be9328 (diff) |
ARM: dts: sunxi: Fix DE2 clocks register range
As it can be seen from DE2 manual, clock range is 0x10000.
Fix it.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Fixes: 73f122c82775 ("ARM: dts: sun8i: a83t: Add display pipeline")
Fixes: 05a43a262d03 ("ARM: dts: sun8i: r40: Add HDMI pipeline")
Fixes: 21b299209330 ("ARM: sun8i: v3s: add device nodes for DE2 display pipeline")
Fixes: d8c6f1f0295c ("ARM: sun8i: h3/h5: add DE2 CCU device node for H3")
[wens@csie.org: added fixes tags]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Diffstat (limited to 'arch/arm/boot/dts/sunxi-h3-h5.dtsi')
-rw-r--r-- | arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index ed3908849111..d5516019e0f6 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -114,7 +114,7 @@ display_clocks: clock@1000000 { /* compatible is in per SoC .dtsi file */ - reg = <0x01000000 0x100000>; + reg = <0x01000000 0x10000>; clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>; clock-names = "bus", |