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authorTony Lindgren <tony@atomide.com>2018-08-08 01:07:05 -0700
committerTony Lindgren <tony@atomide.com>2018-08-17 07:22:56 -0700
commit0ef8e3bb974af56346b34393e643d491d9141c66 (patch)
treedd876e9f7a4d828dcb675656778db0103ae7435d /arch/arm/boot/dts/omap4-droid4-xt894.dts
parent1dbcb97c656eed1a244c960b8b3a469c3d20ce7b (diff)
bus: ti-sysc: Fix module register ioremap for larger offsets
We can have the interconnect target module control registers pretty much anywhere within the module range. The current code attempts an incomplete optimization of the ioremap size but does it wrong and it only works for registers at the beginning of the module. Let's just use the largest control register to calculate the ioremap size. The ioremapped range is for most part cached anyways so there is no need for size optimization. Let's also update the comments accordingly. Fixes: 0eecc636e5a2 ("bus: ti-sysc: Add minimal TI sysc interconnect target driver") Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/omap4-droid4-xt894.dts')
0 files changed, 0 insertions, 0 deletions