Merge tag 'iio-5.7a' of git://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio into staging-next

Jonathan writes:

First set of new IIO device support, fatures and cleanups for the 5.7 cycle

Includes changes for the counter subsystem

Core Feature
* Explicitly handle sysfs values in dB, including correctly handling the
  needed postfix dB.
* Add a TODO to suggest suitable activities for new contributors to IIO now
  the vast majority of drivers are out of staging (and the remaining ones
  there are 'hard'). Also update the TODO in staging to remove stale entries.

Staging graduations
* ad7192 ADC.

New device support
* ad5770r
  - New driver for this 6 channel DAC including DT bindings.
* ad8366
  - Add supprot for the hmc1119 attenuator.
* al3010
  - New driver supporting this Dyna-image light sensors.
  - Power management and DT bindings added in additional patches.
* atlas-sensor
  - Add support for atlas DO-SM device.  Reads disolved oxygen in a solution.
* gpap002x00f
  - New driver and bindings to support the GP2AP002A00F and GP2AP002S00F light
    and proximity sensors. There is some limited existing support in
    input.  The intent is to drop this driver once IIO driver is in place.
* hmc425a
  - New driver for this attenuator.
* icp10100
  - New driver for this presure sensor.
* ltc2632
  - Add support for the ltc2636 8 channel DAC. Includes bindings and some
    tidying up of the driver.
* inv_mpu6050
  - Support IAM20680, ICM20609, ICM20689 and ICM20690.
    Includes related tidy up and rework of low pass filter bandwidth
    handling to give suitable values for all chips.

Binding conversions to yaml or missing bindings docs.
* atlas-sensor, including consolidation of previous 3 separate docs into 1.
* ad7923, previously no doc.
* max1363, split into max1238 and max1363 to simplify yaml.
* stm32-adc

Features
* (counter) 104-quad-8
  - Support a filter clock prescaler.
  - Support reporting of encoder cable status.
* ad7124
  - Low pass filter support.
  - Debugfs interface to access registers directly.
* ad8366
  - Support control of hardware gain.
* inv_mpu6050
  - Runtime pm with autosuspend.
* npcm adc
  - Add reset support. This is a breaking change if DT is not in sync,
    however this device is a BMC so the ecosystem is closed enought that
    this should not be a problem.
* srf04
  - Add power management with DT bindings for the GPIO.
* stm32-timer-trigger
  - Power management.
* (counter) stm32-timer-cnt
  - Power management.
* vcnl4000
  - Enable runtime PM for devices that don't use on demand measurement.

Cleanups and minor fixes
* core
  - Avoid double read when using debugfs.  Whilst we provide no guarantees
    on lack of side effects using the debugfs interfaces, this one is
    generate unexpected results so let us tidy it up.
* dac/Kconfig
  - Alphabetic order.
* ad5755
  - Grammar and minor other fixes.
* ad7124
  - Fail probe if get_voltage fails as no meaningful readings can be had
    without knowing the external reference.
  - Switch to selection between different channel attributes rather than
    building the arrays at runtime.
  - Remove the spi_device_id table as the driver cannot be probled without
    more information that can be provided without dt.
  - Update sysfs docs to provide more inormation and bring remaining docs for
    this part out of staging.
* ad9292
  - Use new SPI transfer delay structure.
* adis library
  - Add unlocked version of adis_initial_startup and refactor the function.
  - Add a product ID santiy check.
  - Add support for different self test registers.
  - Use new SPI delay structure.
  - Add new docs and tidy up existing.
* adis16136
  - Initialize adis_data statically.
* adis16400
  - Initialize adis_data statically.
* adis16460
  - Use core __adis_initial_Startup now it supports everything needed.
* adis16480
  - Initialize adis_data statically.
  - Use core __adis_initial_startup now it supports everything needed.
* al3320a
  - Add missing DT binding docs.
  - Tidy up code formatting.
  - Simplify error paths using devm_add_action_or_reset.
  - Ensure autoloading works by adding the of_match_table.
* atlas-sensor
  - Drop false requirement for interrupt line, the value can be polled using
    a sysfs or hrtimer type trigger.
* exynos-adc
  - Silence warning message on deferring probe.
* gp2ap002
  - Greatly simplify the Lux LUT.
  - Reorder actions around buffer setup and tear down as part of a sub-system
    wide standardization of these.
* inv_mpu6050
  - Various lttle tidyups.
  - Simpliy I2C aux MUX handling by enabling it only at startup. It never
    needs to be disabled.
  - Simplify polling rate when magnetometer enabled by putting only under
    control of userspace.
  - Always execute full reset on devices supporting spi. It does no harm
    when using i2c and makes for simpler code.
  - Reduce over the top sleep times for vddio regulator power up.
  - Greatly simplify power and engine management.
  - Fix some delays in polled reads (only visible due to other changes)
  - Stop preventing sampling rate changes whilst running as there is no
    adverse consequence of doing so.
  - Prevent attempting to read the temperature if neither accel nor
    gyro is enabled.
* lmp9100
  - Reorder actions around buffer setup and tear down as part of a sub-system
    wide standardization of these.
* max1118
  - Use new SPI transfer delay structure.
* mcp320x
  - Use new SPI transfer delay structure.
* si1133
  - Read full 24 bit signed integer instead o dropping last 8 bits of value.
    Not a critical fix as just adds precision.
* st_sensors
  - Use st_sensors_dev_name_probe instead of open coded version in st_accel
  - Handle potential memory allocation failure.
* st_lsm6dsx
  - Fix some wrong structure element naming in documentation.
  - Add missing return value check.
* stm32_timer_cnt
  - Drop some unused left over IIO headers from this count subsystem driver.
  - Ensure the clock is enabled in master mode.  Theoretical issue rather
    than one known to happen in the wild.
* tlc4541
  - Use new SPI delay structure.

* tag 'iio-5.7a' of git://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio: (98 commits)
  iio: dac: Kconfig: sort symbols alphabetically
  iio: light: gp2ap020a00f: fix iio_triggered_buffer_{predisable,postenable} positions
  iio: potentiostat: lmp9100: fix iio_triggered_buffer_{predisable,postenable} positions
  iio: trigger: stm32-timer: add power management support
  iio: trigger: stm32-timer: rename enabled flag
  iio: add a TODO
  counter: 104-quad-8: Support Differential Encoder Cable Status
  counter: 104-quad-8: Support Filter Clock Prescaler
  iio: pressure: icp10100: add driver for InvenSense ICP-101xx
  iio: industrialio-core: Fix debugfs read
  iio: imu: adis: add a note better explaining state_lock
  iio: imu: adis: update 'adis_data' struct doc-string
  iio: imu: adis: add doc-string for 'adis' struct
  iio: imu: adis_buffer: Use new structure for SPI transfer delays
  iio: adc: ti-tlc4541: Use new structure for SPI transfer delays
  iio: adc: mcp320x: Use new structure for SPI transfer delays
  iio: adc: max1118: Use new structure for SPI transfer delays
  iio: adc: ad9292: Use new structure for SPI transfer delays
  iio: adc: exynos: Silence warning about regulators during deferred probe
  staging: iio: update TODO
  ...

1 files changed, 458 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
new file mode 100644
index 000000000000..933ba37944d7
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
@@ -0,0 +1,458 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/bindings/iio/adc/st,stm32-adc.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: STMicroelectronics STM32 ADC bindings
+
+description: |
+  STM32 ADC is a successive approximation analog-to-digital converter.
+  It has several multiplexed input channels. Conversions can be performed
+  in single, continuous, scan or discontinuous mode. Result of the ADC is
+  stored in a left-aligned or right-aligned 32-bit data register.
+  Conversions can be launched in software or using hardware triggers.
+
+  The analog watchdog feature allows the application to detect if the input
+  voltage goes beyond the user-defined, higher or lower thresholds.
+
+  Each STM32 ADC block can have up to 3 ADC instances.
+
+maintainers:
+  - Fabrice Gasnier <fabrice.gasnier@st.com>
+
+properties:
+  compatible:
+    enum:
+      - st,stm32f4-adc-core
+      - st,stm32h7-adc-core
+      - st,stm32mp1-adc-core
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    description: |
+      One or more interrupts for ADC block, depending on part used:
+        - stm32f4 and stm32h7 share a common ADC interrupt line.
+        - stm32mp1 has two separate interrupt lines, one for each ADC within
+          ADC block.
+    minItems: 1
+    maxItems: 2
+
+  clocks:
+    description: |
+      Core can use up to two clocks, depending on part used:
+        - "adc" clock: for the analog circuitry, common to all ADCs.
+          It's required on stm32f4.
+          It's optional on stm32h7 and stm32mp1.
+        - "bus" clock: for registers access, common to all ADCs.
+          It's not present on stm32f4.
+          It's required on stm32h7 and stm32mp1.
+
+  clock-names: true
+
+  st,max-clk-rate-hz:
+    description:
+      Allow to specify desired max clock rate used by analog circuitry.
+
+  vdda-supply:
+    description: Phandle to the vdda input analog voltage.
+
+  vref-supply:
+    description: Phandle to the vref input analog reference voltage.
+
+  booster-supply:
+    description:
+      Phandle to the embedded booster regulator that can be used to supply ADC
+      analog input switches on stm32h7 and stm32mp1.
+
+  vdd-supply:
+    description:
+      Phandle to the vdd input voltage. It can be used to supply ADC analog
+      input switches on stm32mp1.
+
+  st,syscfg:
+    description:
+      Phandle to system configuration controller. It can be used to control the
+      analog circuitry on stm32mp1.
+    allOf:
+      - $ref: "/schemas/types.yaml#/definitions/phandle-array"
+
+  interrupt-controller: true
+
+  '#interrupt-cells':
+    const: 1
+
+  '#address-cells':
+    const: 1
+
+  '#size-cells':
+    const: 0
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: st,stm32f4-adc-core
+
+    then:
+      properties:
+        clocks:
+          maxItems: 1
+
+        clock-names:
+          const: adc
+
+        interrupts:
+          items:
+            - description: interrupt line common for all ADCs
+
+        st,max-clk-rate-hz:
+          minimum: 600000
+          maximum: 36000000
+          default: 36000000
+
+        booster-supply: false
+
+        vdd-supply: false
+
+        st,syscfg: false
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: st,stm32h7-adc-core
+
+    then:
+      properties:
+        clocks:
+          minItems: 1
+          maxItems: 2
+
+        clock-names:
+          items:
+            - const: bus
+            - const: adc
+          minItems: 1
+          maxItems: 2
+
+        interrupts:
+          items:
+            - description: interrupt line common for all ADCs
+
+        st,max-clk-rate-hz:
+          minimum: 120000
+          maximum: 36000000
+          default: 36000000
+
+        vdd-supply: false
+
+        st,syscfg: false
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: st,stm32mp1-adc-core
+
+    then:
+      properties:
+        clocks:
+          minItems: 1
+          maxItems: 2
+
+        clock-names:
+          items:
+            - const: bus
+            - const: adc
+          minItems: 1
+          maxItems: 2
+
+        interrupts:
+          items:
+            - description: interrupt line for ADC1
+            - description: interrupt line for ADC2
+
+        st,max-clk-rate-hz:
+          minimum: 120000
+          maximum: 36000000
+          default: 36000000
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - vdda-supply
+  - vref-supply
+  - interrupt-controller
+  - '#interrupt-cells'
+  - '#address-cells'
+  - '#size-cells'
+
+patternProperties:
+  "^adc@[0-9]+$":
+    type: object
+    description:
+      An ADC block node should contain at least one subnode, representing an
+      ADC instance available on the machine.
+
+    properties:
+      compatible:
+        enum:
+          - st,stm32f4-adc
+          - st,stm32h7-adc
+          - st,stm32mp1-adc
+
+      reg:
+        description: |
+          Offset of ADC instance in ADC block. Valid values are:
+            - 0x0:   ADC1
+            - 0x100: ADC2
+            - 0x200: ADC3 (stm32f4 only)
+        maxItems: 1
+
+      '#io-channel-cells':
+        const: 1
+
+      interrupts:
+        description: |
+          IRQ Line for the ADC instance. Valid values are:
+            - 0 for adc@0
+            - 1 for adc@100
+            - 2 for adc@200 (stm32f4 only)
+        maxItems: 1
+
+      clocks:
+        description:
+          Input clock private to this ADC instance. It's required only on
+          stm32f4, that has per instance clock input for registers access.
+        maxItems: 1
+
+      dmas:
+        description: RX DMA Channel
+        maxItems: 1
+
+      dma-names:
+        const: rx
+
+      assigned-resolution-bits:
+        description: |
+          Resolution (bits) to use for conversions:
+            - can be 6, 8, 10 or 12 on stm32f4
+            - can be 8, 10, 12, 14 or 16 on stm32h7 and stm32mp1
+        allOf:
+          - $ref: /schemas/types.yaml#/definitions/uint32
+
+      st,adc-channels:
+        description: |
+          List of single-ended channels muxed for this ADC. It can have up to:
+            - 16 channels, numbered from 0 to 15 (for in0..in15) on stm32f4
+            - 20 channels, numbered from 0 to 19 (for in0..in19) on stm32h7 and
+              stm32mp1.
+        allOf:
+          - $ref: /schemas/types.yaml#/definitions/uint32-array
+
+      st,adc-diff-channels:
+        description: |
+          List of differential channels muxed for this ADC. Some channels can
+          be configured as differential instead of single-ended on stm32h7 and
+          on stm32mp1. Positive and negative inputs pairs are listed:
+          <vinp vinn>, <vinp vinn>,... vinp and vinn are numbered from 0 to 19.
+
+          Note: At least one of "st,adc-channels" or "st,adc-diff-channels" is
+          required. Both properties can be used together. Some channels can be
+          used as single-ended and some other ones as differential (mixed). But
+          channels can't be configured both as single-ended and differential.
+        allOf:
+          - $ref: /schemas/types.yaml#/definitions/uint32-matrix
+          - items:
+              items:
+                - description: |
+                    "vinp" indicates positive input number
+                  minimum: 0
+                  maximum: 19
+                - description: |
+                    "vinn" indicates negative input number
+                  minimum: 0
+                  maximum: 19
+
+      st,min-sample-time-nsecs:
+        description:
+          Minimum sampling time in nanoseconds. Depending on hardware (board)
+          e.g. high/low analog input source impedance, fine tune of ADC
+          sampling time may be recommended. This can be either one value or an
+          array that matches "st,adc-channels" and/or "st,adc-diff-channels"
+          list, to set sample time resp. for all channels, or independently for
+          each channel.
+        allOf:
+          - $ref: /schemas/types.yaml#/definitions/uint32-array
+
+    allOf:
+      - if:
+          properties:
+            compatible:
+              contains:
+                const: st,stm32f4-adc
+
+        then:
+          properties:
+            reg:
+              enum:
+                - 0x0
+                - 0x100
+                - 0x200
+
+            interrupts:
+              minimum: 0
+              maximum: 2
+
+            assigned-resolution-bits:
+              enum: [6, 8, 10, 12]
+              default: 12
+
+            st,adc-channels:
+              minItems: 1
+              maxItems: 16
+              items:
+                minimum: 0
+                maximum: 15
+
+            st,adc-diff-channels: false
+
+            st,min-sample-time-nsecs:
+              minItems: 1
+              maxItems: 16
+              items:
+                minimum: 80
+
+          required:
+            - clocks
+
+      - if:
+          properties:
+            compatible:
+              contains:
+                enum:
+                  - st,stm32h7-adc
+                  - st,stm32mp1-adc
+
+        then:
+          properties:
+            reg:
+              enum:
+                - 0x0
+                - 0x100
+
+            interrupts:
+              minimum: 0
+              maximum: 1
+
+            assigned-resolution-bits:
+              enum: [8, 10, 12, 14, 16]
+              default: 16
+
+            st,adc-channels:
+              minItems: 1
+              maxItems: 20
+              items:
+                minimum: 0
+                maximum: 19
+
+            st,min-sample-time-nsecs:
+              minItems: 1
+              maxItems: 20
+              items:
+                minimum: 40
+
+    additionalProperties: false
+
+    anyOf:
+      - required:
+          - st,adc-channels
+      - required:
+          - st,adc-diff-channels
+
+    required:
+      - compatible
+      - reg
+      - interrupts
+      - '#io-channel-cells'
+
+examples:
+  - |
+    // Example 1: with stm32f429, ADC1, single-ended channel 8
+      adc123: adc@40012000 {
+        compatible = "st,stm32f4-adc-core";
+        reg = <0x40012000 0x400>;
+        interrupts = <18>;
+        clocks = <&rcc 0 168>;
+        clock-names = "adc";
+        st,max-clk-rate-hz = <36000000>;
+        vdda-supply = <&vdda>;
+        vref-supply = <&vref>;
+        interrupt-controller;
+        #interrupt-cells = <1>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        adc@0 {
+          compatible = "st,stm32f4-adc";
+          #io-channel-cells = <1>;
+          reg = <0x0>;
+          clocks = <&rcc 0 168>;
+          interrupt-parent = <&adc123>;
+          interrupts = <0>;
+          st,adc-channels = <8>;
+          dmas = <&dma2 0 0 0x400 0x0>;
+          dma-names = "rx";
+          assigned-resolution-bits = <8>;
+        };
+        // ...
+        // other adc child nodes follow...
+      };
+
+  - |
+    // Example 2: with stm32mp157c to setup ADC1 with:
+    // - channels 0 & 1 as single-ended
+    // - channels 2 & 3 as differential (with resp. 6 & 7 negative inputs)
+      #include <dt-bindings/interrupt-controller/arm-gic.h>
+      #include <dt-bindings/clock/stm32mp1-clks.h>
+      adc12: adc@48003000 {
+        compatible = "st,stm32mp1-adc-core";
+        reg = <0x48003000 0x400>;
+        interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&rcc ADC12>, <&rcc ADC12_K>;
+        clock-names = "bus", "adc";
+        booster-supply = <&booster>;
+        vdd-supply = <&vdd>;
+        vdda-supply = <&vdda>;
+        vref-supply = <&vref>;
+        st,syscfg = <&syscfg>;
+        interrupt-controller;
+        #interrupt-cells = <1>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        adc@0 {
+          compatible = "st,stm32mp1-adc";
+          #io-channel-cells = <1>;
+          reg = <0x0>;
+          interrupt-parent = <&adc12>;
+          interrupts = <0>;
+          st,adc-channels = <0 1>;
+          st,adc-diff-channels = <2 6>, <3 7>;
+          st,min-sample-time-nsecs = <5000>;
+          dmas = <&dmamux1 9 0x400 0x05>;
+          dma-names = "rx";
+        };
+        // ...
+        // other adc child node follow...
+      };
+
+...