diff options
author | Ulrich Hecht <ulrich.hecht+renesas@gmail.com> | 2014-12-17 17:18:49 +0100 |
---|---|---|
committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2015-01-08 16:14:30 +0100 |
commit | 596bdcf7782899d699c13aad7b20f1d99810d1fa (patch) | |
tree | 61f965a1ef5034d19496b439199fd08dc00cb26f /Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt | |
parent | caa9657085bd1fcc8e5ba8f21799c75a4d8a70b5 (diff) |
clk: shmobile: r8a73a4 common clock framework implementation
Driver for the R8A73A4's clocks that are too specific to be supported by a
generic driver.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Michael Turquette <mturquette@linaro.org>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt')
-rw-r--r-- | Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt new file mode 100644 index 000000000000..ece92393e80d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,r8a73a4-cpg-clocks.txt @@ -0,0 +1,33 @@ +* Renesas R8A73A4 Clock Pulse Generator (CPG) + +The CPG generates core clocks for the R8A73A4 SoC. It includes five PLLs +and several fixed ratio dividers. + +Required Properties: + + - compatible: Must be "renesas,r8a73a4-cpg-clocks" + + - reg: Base address and length of the memory resource used by the CPG + + - clocks: Reference to the parent clocks ("extal1" and "extal2") + + - #clock-cells: Must be 1 + + - clock-output-names: The names of the clocks. Supported clocks are "main", + "pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b", + "m1", "m2", "zx", "zs", and "hp". + + +Example +------- + + cpg_clocks: cpg_clocks@e6150000 { + compatible = "renesas,r8a73a4-cpg-clocks"; + reg = <0 0xe6150000 0 0x10000>; + clocks = <&extal1_clk>, <&extal2_clk>; + #clock-cells = <1>; + clock-output-names = "main", "pll0", "pll1", "pll2", + "pll2s", "pll2h", "z", "z2", + "i", "m3", "b", "m1", "m2", + "zx", "zs", "hp"; + }; |