Merge tag 'devicetree-for-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

Pull Devicetree updates from Rob Herring:

 - Improve device links cycle detection and breaking. Add more bindings
   for device link dependencies.

 - Refactor parsing 'no-map' in __reserved_mem_alloc_size()

 - Improve DT unittest 'ranges' and 'dma-ranges' test case to check
   differing cell sizes

 - Various http to https link conversions

 - Add a schema check to prevent 'syscon' from being used by itself
   without a more specific compatible

 - A bunch more DT binding conversions to schema

* tag 'devicetree-for-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (55 commits)
  of: reserved-memory: remove duplicated call to of_get_flat_dt_prop() for no-map node
  of: unittest: Use bigger address cells to catch parser regressions
  dt-bindings: memory-controllers: Convert mmdc to json-schema
  dt-bindings: mtd: Convert imx nand to json-schema
  dt-bindings: mtd: Convert gpmi nand to json-schema
  dt-bindings: iio: io-channel-mux: Fix compatible string in example code
  of: property: Add device link support for pinctrl-0 through pinctrl-8
  of: property: Add device link support for multiple DT bindings
  dt-bindings: phy: ti: phy-gmii-sel: convert bindings to json-schema
  dt-bindings: mux: mux.h: drop a duplicated word
  dt-bindings: misc: Convert olpc,xo1.75-ec to json-schema
  dt-bindings: aspeed-lpc: Replace HTTP links with HTTPS ones
  dt-bindings: drm/bridge: Replace HTTP links with HTTPS ones
  drm/tilcdc: Replace HTTP links with HTTPS ones
  dt-bindings: iommu: renesas,ipmmu-vmsa: Add r8a774e1 support
  dt-bindings: fpga: Replace HTTP links with HTTPS ones
  dt-bindings: virtio: Replace HTTP links with HTTPS ones
  dt-bindings: media: imx274: Add optional input clock and supplies
  dt-bindings: i2c-gpio: Use 'deprecated' keyword on deprecated properties
  dt-bindings: interrupt-controller: Fix typos in loongson,liointc.yaml
  ...

1 files changed, 0 insertions, 103 deletions

diff --git a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
deleted file mode 100644
index 93d89adb7afe..000000000000
--- a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt
+++ /dev/null
@@ -1,103 +0,0 @@
-* Clock bindings for Freescale i.MX7ULP
-
-i.MX7ULP Clock functions are under joint control of the System
-Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
-modules, and Core Mode Controller (CMC)1 blocks
-
-The clocking scheme provides clear separation between M4 domain
-and A7 domain. Except for a few clock sources shared between two
-domains, such as the System Oscillator clock, the Slow IRC (SIRC),
-and and the Fast IRC clock (FIRCLK), clock sources and clock
-management are separated and contained within each domain.
-
-M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
-A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
-
-Note: this binding doc is only for A7 clock domain.
-
-System Clock Generation (SCG) modules:
----------------------------------------------------------------------
-The System Clock Generation (SCG) is responsible for clock generation
-and distribution across this device. Functions performed by the SCG
-include: clock reference selection, generation of clock used to derive
-processor, system, peripheral bus and external memory interface clocks,
-source selection for peripheral clocks and control of power saving
-clock gating mode.
-
-Required properties:
-
-- compatible:	Should be "fsl,imx7ulp-scg1".
-- reg : 	Should contain registers location and length.
-- #clock-cells:	Should be <1>.
-- clocks:	Should contain the fixed input clocks.
-- clock-names:  Should contain the following clock names:
-		"rosc", "sosc", "sirc", "firc", "upll", "mpll".
-
-Peripheral Clock Control (PCC) modules:
----------------------------------------------------------------------
-The Peripheral Clock Control (PCC) is responsible for clock selection,
-optional division and clock gating mode for peripherals in their
-respected power domain
-
-Required properties:
-- compatible:	Should be one of:
-		  "fsl,imx7ulp-pcc2",
-		  "fsl,imx7ulp-pcc3".
-- reg : 	Should contain registers location and length.
-- #clock-cells:	Should be <1>.
-- clocks:	Should contain the fixed input clocks.
-- clock-names:  Should contain the following clock names:
-		"nic1_bus_clk", "nic1_clk", "ddr_clk", "apll_pfd2",
-		"apll_pfd1", "apll_pfd0", "upll", "sosc_bus_clk",
-		"mpll", "firc_bus_clk", "rosc", "spll_bus_clk";
-
-The clock consumer should specify the desired clock by having the clock
-ID in its "clocks" phandle cell.
-See include/dt-bindings/clock/imx7ulp-clock.h
-for the full list of i.MX7ULP clock IDs of each module.
-
-Examples:
-
-#include <dt-bindings/clock/imx7ulp-clock.h>
-
-scg1: scg1@403e0000 {
-	compatible = "fsl,imx7ulp-scg1;
-	reg = <0x403e0000 0x10000>;
-	clocks = <&rosc>, <&sosc>, <&sirc>,
-		 <&firc>, <&upll>, <&mpll>;
-	clock-names = "rosc", "sosc", "sirc",
-		      "firc", "upll", "mpll";
-	#clock-cells = <1>;
-};
-
-pcc2: pcc2@403f0000 {
-	compatible = "fsl,imx7ulp-pcc2";
-	reg = <0x403f0000 0x10000>;
-	#clock-cells = <1>;
-	clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
-		 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
-		 <&scg1 IMX7ULP_CLK_DDR_DIV>,
-		 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
-		 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
-		 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
-		 <&scg1 IMX7ULP_CLK_UPLL>,
-		 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
-		 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
-		 <&scg1 IMX7ULP_CLK_ROSC>,
-		 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
-	clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
-		      "apll_pfd2", "apll_pfd1", "apll_pfd0",
-		      "upll", "sosc_bus_clk", "mpll",
-		      "firc_bus_clk", "rosc", "spll_bus_clk";
-};
-
-usdhc1: usdhc@40380000 {
-	compatible = "fsl,imx7ulp-usdhc";
-	reg = <0x40380000 0x10000>;
-	interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
-	clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
-		 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
-		 <&pcc2 IMX7ULP_CLK_USDHC1>;
-	clock-names ="ipg", "ahb", "per";
-	bus-width = <4>;
-};