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authorMark Brown <broonie@kernel.org>2018-08-10 17:31:24 +0100
committerMark Brown <broonie@kernel.org>2018-08-10 17:31:24 +0100
commitd22d59362b7b2c749245f1269d447011c76ca41d (patch)
treeb3fc0673f62394dc5ed417eac6bad485a28baf25 /Documentation/devicetree/bindings/arm
parenta8afa92ec0d9312b23fd291aa8db95da266f2d5f (diff)
parent46fc033eba42f5a4fb583b2ab53f0a9918468452 (diff)
Merge branch 'regulator-4.19' into regulator-next
Diffstat (limited to 'Documentation/devicetree/bindings/arm')
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+== Introduction==
+
+LLCC (Last Level Cache Controller) provides last level of cache memory in SOC,
+that can be shared by multiple clients. Clients here are different cores in the
+SOC, the idea is to minimize the local caches at the clients and migrate to
+common pool of memory. Cache memory is divided into partitions called slices
+which are assigned to clients. Clients can query the slice details, activate
+and deactivate them.
+
+Properties:
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be "qcom,sdm845-llcc"
+
+- reg:
+ Usage: required
+ Value Type: <prop-encoded-array>
+ Definition: Start address and the the size of the register region.
+
+Example:
+
+ cache-controller@1100000 {
+ compatible = "qcom,sdm845-llcc";
+ reg = <0x1100000 0x250000>;
+ };