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authorShukun Tan <tanshukun1@huawei.com>2020-05-15 17:14:00 +0800
committerHerbert Xu <herbert@gondor.apana.org.au>2020-05-23 00:08:23 +1000
commit988453fb2f18be3f3915220e4c6f18018186aa89 (patch)
tree741a6dcb77de54f498c6fdef81814bea100c99a7 /Documentation/ABI/testing/debugfs-hisi-hpre
parentc31dc9fe165d1b53c0494e0260a798d491de7bb4 (diff)
crypto: hisilicon/qm - change debugfs file name from qm_regs to regs
The debugfs qm_regs file is already in the qm directory, so no qm_ prefix is required. Signed-off-by: Shukun Tan <tanshukun1@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'Documentation/ABI/testing/debugfs-hisi-hpre')
-rw-r--r--Documentation/ABI/testing/debugfs-hisi-hpre6
1 files changed, 3 insertions, 3 deletions
diff --git a/Documentation/ABI/testing/debugfs-hisi-hpre b/Documentation/ABI/testing/debugfs-hisi-hpre
index 1fe3eae8ab21..b4be5f1db4b7 100644
--- a/Documentation/ABI/testing/debugfs-hisi-hpre
+++ b/Documentation/ABI/testing/debugfs-hisi-hpre
@@ -33,7 +33,7 @@ Contact: linux-crypto@vger.kernel.org
Description: Dump debug registers from the HPRE.
Only available for PF.
-What: /sys/kernel/debug/hisi_hpre/<bdf>/qm/qm_regs
+What: /sys/kernel/debug/hisi_hpre/<bdf>/qm/regs
Date: Sep 2019
Contact: linux-crypto@vger.kernel.org
Description: Dump debug registers from the QM.
@@ -44,13 +44,13 @@ What: /sys/kernel/debug/hisi_hpre/<bdf>/qm/current_q
Date: Sep 2019
Contact: linux-crypto@vger.kernel.org
Description: One QM may contain multiple queues. Select specific queue to
- show its debug registers in above qm_regs.
+ show its debug registers in above regs.
Only available for PF.
What: /sys/kernel/debug/hisi_hpre/<bdf>/qm/clear_enable
Date: Sep 2019
Contact: linux-crypto@vger.kernel.org
-Description: QM debug registers(qm_regs) read clear control. 1 means enable
+Description: QM debug registers(regs) read clear control. 1 means enable
register read clear, otherwise 0.
Writing to this file has no functional effect, only enable or
disable counters clear after reading of these registers.