MIPS: Octeon: Remove unused SLI types and macros.

Remove all unused bitfields and macros. Convert the remaining
bitfields to use __BITFIELD_FIELD instead of #ifdef.

[ralf@linux-mips.org: Add inclusions of <uapi/asm/bitfield.h> as necessary.]

Signed-off-by: Steven J. Hill <steven.hill@cavium.com>
Acked-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/15405/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

2 files changed, 76 insertions, 3469 deletions

diff --git a/arch/mips/include/asm/octeon/cvmx-sli-defs.h b/arch/mips/include/asm/octeon/cvmx-sli-defs.h
index e697c2f52a62..52cf96ea43e5 100644
--- a/arch/mips/include/asm/octeon/cvmx-sli-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-sli-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2012 Cavium Networks
+ * Copyright (c) 2003-2017 Cavium, Inc.
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -28,3494 +28,101 @@
 #ifndef __CVMX_SLI_DEFS_H__
 #define __CVMX_SLI_DEFS_H__
 
-#define CVMX_SLI_BIST_STATUS (0x0000000000000580ull)
-#define CVMX_SLI_CTL_PORTX(offset) (0x0000000000000050ull + ((offset) & 3) * 16)
-#define CVMX_SLI_CTL_STATUS (0x0000000000000570ull)
-#define CVMX_SLI_DATA_OUT_CNT (0x00000000000005F0ull)
-#define CVMX_SLI_DBG_DATA (0x0000000000000310ull)
-#define CVMX_SLI_DBG_SELECT (0x0000000000000300ull)
-#define CVMX_SLI_DMAX_CNT(offset) (0x0000000000000400ull + ((offset) & 1) * 16)
-#define CVMX_SLI_DMAX_INT_LEVEL(offset) (0x00000000000003E0ull + ((offset) & 1) * 16)
-#define CVMX_SLI_DMAX_TIM(offset) (0x0000000000000420ull + ((offset) & 1) * 16)
-#define CVMX_SLI_INT_ENB_CIU (0x0000000000003CD0ull)
-#define CVMX_SLI_INT_ENB_PORTX(offset) (0x0000000000000340ull + ((offset) & 1) * 16)
-#define CVMX_SLI_INT_SUM (0x0000000000000330ull)
-#define CVMX_SLI_LAST_WIN_RDATA0 (0x0000000000000600ull)
-#define CVMX_SLI_LAST_WIN_RDATA1 (0x0000000000000610ull)
-#define CVMX_SLI_LAST_WIN_RDATA2 (0x00000000000006C0ull)
-#define CVMX_SLI_LAST_WIN_RDATA3 (0x00000000000006D0ull)
-#define CVMX_SLI_MAC_CREDIT_CNT (0x0000000000003D70ull)
-#define CVMX_SLI_MAC_CREDIT_CNT2 (0x0000000000003E10ull)
-#define CVMX_SLI_MAC_NUMBER (0x0000000000003E00ull)
-#define CVMX_SLI_MEM_ACCESS_CTL (0x00000000000002F0ull)
-#define CVMX_SLI_MEM_ACCESS_SUBIDX(offset) (0x00000000000000E0ull + ((offset) & 31) * 16 - 16*12)
-#define CVMX_SLI_MSI_ENB0 (0x0000000000003C50ull)
-#define CVMX_SLI_MSI_ENB1 (0x0000000000003C60ull)
-#define CVMX_SLI_MSI_ENB2 (0x0000000000003C70ull)
-#define CVMX_SLI_MSI_ENB3 (0x0000000000003C80ull)
-#define CVMX_SLI_MSI_RCV0 (0x0000000000003C10ull)
-#define CVMX_SLI_MSI_RCV1 (0x0000000000003C20ull)
-#define CVMX_SLI_MSI_RCV2 (0x0000000000003C30ull)
-#define CVMX_SLI_MSI_RCV3 (0x0000000000003C40ull)
-#define CVMX_SLI_MSI_RD_MAP (0x0000000000003CA0ull)
-#define CVMX_SLI_MSI_W1C_ENB0 (0x0000000000003CF0ull)
-#define CVMX_SLI_MSI_W1C_ENB1 (0x0000000000003D00ull)
-#define CVMX_SLI_MSI_W1C_ENB2 (0x0000000000003D10ull)
-#define CVMX_SLI_MSI_W1C_ENB3 (0x0000000000003D20ull)
-#define CVMX_SLI_MSI_W1S_ENB0 (0x0000000000003D30ull)
-#define CVMX_SLI_MSI_W1S_ENB1 (0x0000000000003D40ull)
-#define CVMX_SLI_MSI_W1S_ENB2 (0x0000000000003D50ull)
-#define CVMX_SLI_MSI_W1S_ENB3 (0x0000000000003D60ull)
-#define CVMX_SLI_MSI_WR_MAP (0x0000000000003C90ull)
-#define CVMX_SLI_PCIE_MSI_RCV (0x0000000000003CB0ull)
-#define CVMX_SLI_PCIE_MSI_RCV_B1 (0x0000000000000650ull)
-#define CVMX_SLI_PCIE_MSI_RCV_B2 (0x0000000000000660ull)
-#define CVMX_SLI_PCIE_MSI_RCV_B3 (0x0000000000000670ull)
-#define CVMX_SLI_PKTX_CNTS(offset) (0x0000000000002400ull + ((offset) & 31) * 16)
-#define CVMX_SLI_PKTX_INSTR_BADDR(offset) (0x0000000000002800ull + ((offset) & 31) * 16)
-#define CVMX_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (0x0000000000002C00ull + ((offset) & 31) * 16)
-#define CVMX_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (0x0000000000003000ull + ((offset) & 31) * 16)
-#define CVMX_SLI_PKTX_INSTR_HEADER(offset) (0x0000000000003400ull + ((offset) & 31) * 16)
-#define CVMX_SLI_PKTX_IN_BP(offset) (0x0000000000003800ull + ((offset) & 31) * 16)
-#define CVMX_SLI_PKTX_OUT_SIZE(offset) (0x0000000000000C00ull + ((offset) & 31) * 16)
-#define CVMX_SLI_PKTX_SLIST_BADDR(offset) (0x0000000000001400ull + ((offset) & 31) * 16)
-#define CVMX_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (0x0000000000001800ull + ((offset) & 31) * 16)
-#define CVMX_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (0x0000000000001C00ull + ((offset) & 31) * 16)
-#define CVMX_SLI_PKT_CNT_INT (0x0000000000001130ull)
-#define CVMX_SLI_PKT_CNT_INT_ENB (0x0000000000001150ull)
-#define CVMX_SLI_PKT_CTL (0x0000000000001220ull)
-#define CVMX_SLI_PKT_DATA_OUT_ES (0x00000000000010B0ull)
-#define CVMX_SLI_PKT_DATA_OUT_NS (0x00000000000010A0ull)
-#define CVMX_SLI_PKT_DATA_OUT_ROR (0x0000000000001090ull)
-#define CVMX_SLI_PKT_DPADDR (0x0000000000001080ull)
-#define CVMX_SLI_PKT_INPUT_CONTROL (0x0000000000001170ull)
-#define CVMX_SLI_PKT_INSTR_ENB (0x0000000000001000ull)
-#define CVMX_SLI_PKT_INSTR_RD_SIZE (0x00000000000011A0ull)
-#define CVMX_SLI_PKT_INSTR_SIZE (0x0000000000001020ull)
-#define CVMX_SLI_PKT_INT_LEVELS (0x0000000000001120ull)
-#define CVMX_SLI_PKT_IN_BP (0x0000000000001210ull)
-#define CVMX_SLI_PKT_IN_DONEX_CNTS(offset) (0x0000000000002000ull + ((offset) & 31) * 16)
-#define CVMX_SLI_PKT_IN_INSTR_COUNTS (0x0000000000001200ull)
-#define CVMX_SLI_PKT_IN_PCIE_PORT (0x00000000000011B0ull)
-#define CVMX_SLI_PKT_IPTR (0x0000000000001070ull)
-#define CVMX_SLI_PKT_OUTPUT_WMARK (0x0000000000001180ull)
-#define CVMX_SLI_PKT_OUT_BMODE (0x00000000000010D0ull)
-#define CVMX_SLI_PKT_OUT_BP_EN (0x0000000000001240ull)
-#define CVMX_SLI_PKT_OUT_ENB (0x0000000000001010ull)
-#define CVMX_SLI_PKT_PCIE_PORT (0x00000000000010E0ull)
-#define CVMX_SLI_PKT_PORT_IN_RST (0x00000000000011F0ull)
-#define CVMX_SLI_PKT_SLIST_ES (0x0000000000001050ull)
-#define CVMX_SLI_PKT_SLIST_NS (0x0000000000001040ull)
-#define CVMX_SLI_PKT_SLIST_ROR (0x0000000000001030ull)
-#define CVMX_SLI_PKT_TIME_INT (0x0000000000001140ull)
-#define CVMX_SLI_PKT_TIME_INT_ENB (0x0000000000001160ull)
-#define CVMX_SLI_PORTX_PKIND(offset) (0x0000000000000800ull + ((offset) & 31) * 16)
-#define CVMX_SLI_S2M_PORTX_CTL(offset) (0x0000000000003D80ull + ((offset) & 3) * 16)
-#define CVMX_SLI_SCRATCH_1 (0x00000000000003C0ull)
-#define CVMX_SLI_SCRATCH_2 (0x00000000000003D0ull)
-#define CVMX_SLI_STATE1 (0x0000000000000620ull)
-#define CVMX_SLI_STATE2 (0x0000000000000630ull)
-#define CVMX_SLI_STATE3 (0x0000000000000640ull)
-#define CVMX_SLI_TX_PIPE (0x0000000000001230ull)
-#define CVMX_SLI_WINDOW_CTL (0x00000000000002E0ull)
-#define CVMX_SLI_WIN_RD_ADDR (0x0000000000000010ull)
-#define CVMX_SLI_WIN_RD_DATA (0x0000000000000040ull)
-#define CVMX_SLI_WIN_WR_ADDR (0x0000000000000000ull)
-#define CVMX_SLI_WIN_WR_DATA (0x0000000000000020ull)
-#define CVMX_SLI_WIN_WR_MASK (0x0000000000000030ull)
+#include <uapi/asm/bitfield.h>
+
+#define CVMX_SLI_PCIE_MSI_RCV CVMX_SLI_PCIE_MSI_RCV_FUNC()
+static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_FUNC(void)
+{
+	switch (cvmx_get_octeon_family()) {
+	case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+	case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
+		return 0x0000000000003CB0ull;
+	case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
+	case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
+	case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
+		if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
+			return 0x0000000000003CB0ull;
+	default:
+		return 0x0000000000023CB0ull;
+	}
+}
 
-union cvmx_sli_bist_status {
-	uint64_t u64;
-	struct cvmx_sli_bist_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-		uint64_t reserved_32_63:32;
-		uint64_t ncb_req:1;
-		uint64_t n2p0_c:1;
-		uint64_t n2p0_o:1;
-		uint64_t n2p1_c:1;
-		uint64_t n2p1_o:1;
-		uint64_t cpl_p0:1;
-		uint64_t cpl_p1:1;
-		uint64_t reserved_19_24:6;
-		uint64_t p2n0_c0:1;
-		uint64_t p2n0_c1:1;
-		uint64_t p2n0_n:1;
-		uint64_t p2n0_p0:1;
-		uint64_t p2n0_p1:1;
-		uint64_t p2n1_c0:1;
-		uint64_t p2n1_c1:1;
-		uint64_t p2n1_n:1;
-		uint64_t p2n1_p0:1;
-		uint64_t p2n1_p1:1;
-		uint64_t reserved_6_8:3;
-		uint64_t dsi1_1:1;
-		uint64_t dsi1_0:1;
-		uint64_t dsi0_1:1;
-		uint64_t dsi0_0:1;
-		uint64_t msi:1;
-		uint64_t ncb_cmd:1;
-#else
-		uint64_t ncb_cmd:1;
-		uint64_t msi:1;
-		uint64_t dsi0_0:1;
-		uint64_t dsi0_1:1;
-		uint64_t dsi1_0:1;
-		uint64_t dsi1_1:1;
-		uint64_t reserved_6_8:3;
-		uint64_t p2n1_p1:1;
-		uint64_t p2n1_p0:1;
-		uint64_t p2n1_n:1;
-		uint64_t p2n1_c1:1;
-		uint64_t p2n1_c0:1;
-		uint64_t p2n0_p1:1;
-		uint64_t p2n0_p0:1;
-		uint64_t p2n0_n:1;
-		uint64_t p2n0_c1:1;
-		uint64_t p2n0_c0:1;
-		uint64_t reserved_19_24:6;
-		uint64_t cpl_p1:1;
-		uint64_t cpl_p0:1;
-		uint64_t n2p1_o:1;
-		uint64_t n2p1_c:1;
-		uint64_t n2p0_o:1;
-		uint64_t n2p0_c:1;
-		uint64_t ncb_req:1;
-		uint64_t reserved_32_63:32;
-#endif
-	} s;
-	struct cvmx_sli_bist_status_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-		uint64_t reserved_31_63:33;
-		uint64_t n2p0_c:1;
-		uint64_t n2p0_o:1;
-		uint64_t reserved_27_28:2;
-		uint64_t cpl_p0:1;
-		uint64_t cpl_p1:1;
-		uint64_t reserved_19_24:6;
-		uint64_t p2n0_c0:1;
-		uint64_t p2n0_c1:1;
-		uint64_t p2n0_n:1;
-		uint64_t p2n0_p0:1;
-		uint64_t p2n0_p1:1;
-		uint64_t p2n1_c0:1;
-		uint64_t p2n1_c1:1;
-		uint64_t p2n1_n:1;
-		uint64_t p2n1_p0:1;
-		uint64_t p2n1_p1:1;
-		uint64_t reserved_6_8:3;
-		uint64_t dsi1_1:1;
-		uint64_t dsi1_0:1;
-		uint64_t dsi0_1:1;
-		uint64_t dsi0_0:1;
-		uint64_t msi:1;
-		uint64_t ncb_cmd:1;
-#else
-		uint64_t ncb_cmd:1;
-		uint64_t msi:1;
-		uint64_t dsi0_0:1;
-		uint64_t dsi0_1:1;
-		uint64_t dsi1_0:1;
-		uint64_t dsi1_1:1;
-		uint64_t reserved_6_8:3;
-		uint64_t p2n1_p1:1;
-		uint64_t p2n1_p0:1;
-		uint64_t p2n1_n:1;
-		uint64_t p2n1_c1:1;
-		uint64_t p2n1_c0:1;
-		uint64_t p2n0_p1:1;
-		uint64_t p2n0_p0:1;
-		uint64_t p2n0_n:1;
-		uint64_t p2n0_c1:1;
-		uint64_t p2n0_c0:1;
-		uint64_t reserved_19_24:6;
-		uint64_t cpl_p1:1;
-		uint64_t cpl_p0:1;
-		uint64_t reserved_27_28:2;
-		uint64_t n2p0_o:1;
-		uint64_t n2p0_c:1;
-		uint64_t reserved_31_63:33;
-#endif
-	} cn61xx;
-	struct cvmx_sli_bist_status_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-		uint64_t reserved_31_63:33;
-		uint64_t n2p0_c:1;
-		uint64_t n2p0_o:1;
-		uint64_t n2p1_c:1;
-		uint64_t n2p1_o:1;
-		uint64_t cpl_p0:1;
-		uint64_t cpl_p1:1;
-		uint64_t reserved_19_24:6;
-		uint64_t p2n0_c0:1;
-		uint64_t p2n0_c1:1;
-		uint64_t p2n0_n:1;
-		uint64_t p2n0_p0:1;
-		uint64_t p2n0_p1:1;
-		uint64_t p2n1_c0:1;
-		uint64_t p2n1_c1:1;
-		uint64_t p2n1_n:1;
-		uint64_t p2n1_p0:1;
-		uint64_t p2n1_p1:1;
-		uint64_t reserved_6_8:3;
-		uint64_t dsi1_1:1;
-		uint64_t dsi1_0:1;
-		uint64_t dsi0_1:1;
-		uint64_t dsi0_0:1;
-		uint64_t msi:1;
-		uint64_t ncb_cmd:1;
-#else
-		uint64_t ncb_cmd:1;
-		uint64_t msi:1;
-		uint64_t dsi0_0:1;
-		uint64_t dsi0_1:1;
-		uint64_t dsi1_0:1;
-		uint64_t dsi1_1:1;
-		uint64_t reserved_6_8:3;
-		uint64_t p2n1_p1:1;
-		uint64_t p2n1_p0:1;
-		uint64_t p2n1_n:1;
-		uint64_t p2n1_c1:1;
-		uint64_t p2n1_c0:1;
-		uint64_t p2n0_p1:1;
-		uint64_t p2n0_p0:1;
-		uint64_t p2n0_n:1;
-		uint64_t p2n0_c1:1;
-		uint64_t p2n0_c0:1;
-		uint64_t reserved_19_24:6;
-		uint64_t cpl_p1:1;
-		uint64_t cpl_p0:1;
-		uint64_t n2p1_o:1;
-		uint64_t n2p1_c:1;
-		uint64_t n2p0_o:1;
-		uint64_t n2p0_c:1;
-		uint64_t reserved_31_63:33;
-#endif
-	} cn63xx;
-	struct cvmx_sli_bist_status_cn63xx cn63xxp1;
-	struct cvmx_sli_bist_status_cn61xx cn66xx;
-	struct cvmx_sli_bist_status_s cn68xx;
-	struct cvmx_sli_bist_status_s cn68xxp1;
-	struct cvmx_sli_bist_status_cn61xx cnf71xx;
-};
 
 union cvmx_sli_ctl_portx {
 	uint64_t u64;
 	struct cvmx_sli_ctl_portx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-		uint64_t reserved_22_63:42;
-		uint64_t intd:1;
-		uint64_t intc:1;
-		uint64_t intb:1;
-		uint64_t inta:1;
-		uint64_t dis_port:1;
-		uint64_t waitl_com:1;
-		uint64_t intd_map:2;
-		uint64_t intc_map:2;
-		uint64_t intb_map:2;
-		uint64_t inta_map:2;
-		uint64_t ctlp_ro:1;
-		uint64_t reserved_6_6:1;
-		uint64_t ptlp_ro:1;
-		uint64_t reserved_1_4:4;
-		uint64_t wait_com:1;
-#else
-		uint64_t wait_com:1;
-		uint64_t reserved_1_4:4;
-		uint64_t ptlp_ro:1;
-		uint64_t reserved_6_6:1;
-		uint64_t ctlp_ro:1;
-		uint64_t inta_map:2;
-		uint64_t intb_map:2;
-		uint64_t intc_map:2;
-		uint64_t intd_map:2;
-		uint64_t waitl_com:1;
-		uint64_t dis_port:1;
-		uint64_t inta:1;
-		uint64_t intb:1;
-		uint64_t intc:1;
-		uint64_t intd:1;
-		uint64_t reserved_22_63:42;
-#endif
-	} s;
-	struct cvmx_sli_ctl_portx_s cn61xx;
-	struct cvmx_sli_ctl_portx_s cn63xx;
-	struct cvmx_sli_ctl_portx_s cn63xxp1;
-	struct cvmx_sli_ctl_portx_s cn66xx;
-	struct cvmx_sli_ctl_portx_s cn68xx;
-	struct cvmx_sli_ctl_portx_s cn68xxp1;
-	struct cvmx_sli_ctl_portx_s cnf71xx;
-};
-
-union cvmx_sli_ctl_status {
-	uint64_t u64;
-	struct cvmx_sli_ctl_status_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-		uint64_t reserved_20_63:44;
-		uint64_t p1_ntags:6;
-		uint64_t p0_ntags:6;
-		uint64_t chip_rev:8;
-#else
-		uint64_t chip_rev:8;
-		uint64_t p0_ntags:6;
-		uint64_t p1_ntags:6;
-		uint64_t reserved_20_63:44;
-#endif
-	} s;
-	struct cvmx_sli_ctl_status_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-		uint64_t reserved_14_63:50;
-		uint64_t p0_ntags:6;
-		uint64_t chip_rev:8;
-#else
-		uint64_t chip_rev:8;
-		uint64_t p0_ntags:6;
-		uint64_t reserved_14_63:50;
-#endif
-	} cn61xx;
-	struct cvmx_sli_ctl_status_s cn63xx;
-	struct cvmx_sli_ctl_status_s cn63xxp1;
-	struct cvmx_sli_ctl_status_cn61xx cn66xx;
-	struct cvmx_sli_ctl_status_s cn68xx;
-	struct cvmx_sli_ctl_status_s cn68xxp1;
-	struct cvmx_sli_ctl_status_cn61xx cnf71xx;
-};
-
-union cvmx_sli_data_out_cnt {
-	uint64_t u64;
-	struct cvmx_sli_data_out_cnt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-		uint64_t reserved_44_63:20;
-		uint64_t p1_ucnt:16;
-		uint64_t p1_fcnt:6;
-		uint64_t p0_ucnt:16;
-		uint64_t p0_fcnt:6;
-#else
-		uint64_t p0_fcnt:6;
-		uint64_t p0_ucnt:16;
-		uint64_t p1_fcnt:6;
-		uint64_t p1_ucnt:16;
-		uint64_t reserved_44_63:20;
-#endif
-	} s;
-	struct cvmx_sli_data_out_cnt_s cn61xx;
-	struct cvmx_sli_data_out_cnt_s cn63xx;
-	struct cvmx_sli_data_out_cnt_s cn63xxp1;
-	struct cvmx_sli_data_out_cnt_s cn66xx;
-	struct cvmx_sli_data_out_cnt_s cn68xx;
-	struct cvmx_sli_data_out_cnt_s cn68xxp1;
-	struct cvmx_sli_data_out_cnt_s cnf71xx;
-};
-
-union cvmx_sli_dbg_data {
-	uint64_t u64;
-	struct cvmx_sli_dbg_data_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-		uint64_t reserved_18_63:46;
-		uint64_t dsel_ext:1;
-		uint64_t data:17;
-#else
-		uint64_t data:17;
-		uint64_t dsel_ext:1;
-		uint64_t reserved_18_63:46;
-#endif
-	} s;
-	struct cvmx_sli_dbg_data_s cn61xx;
-	struct cvmx_sli_dbg_data_s cn63xx;
-	struct cvmx_sli_dbg_data_s cn63xxp1;
-	struct cvmx_sli_dbg_data_s cn66xx;
-	struct cvmx_sli_dbg_data_s cn68xx;
-	struct cvmx_sli_dbg_data_s cn68xxp1;
-	struct cvmx_sli_dbg_data_s cnf71xx;
-};
-
-union cvmx_sli_dbg_select {
-	uint64_t u64;
-	struct cvmx_sli_dbg_select_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-		uint64_t reserved_33_63:31;
-		uint64_t adbg_sel:1;
-		uint64_t dbg_sel:32;
-#else
-		uint64_t dbg_sel:32;
-		uint64_t adbg_sel:1;
-		uint64_t reserved_33_63:31;
-#endif
-	} s;
-	struct cvmx_sli_dbg_select_s cn61xx;
-	struct cvmx_sli_dbg_select_s cn63xx;
-	struct cvmx_sli_dbg_select_s cn63xxp1;
-	struct cvmx_sli_dbg_select_s cn66xx;
-	struct cvmx_sli_dbg_select_s cn68xx;
-	struct cvmx_sli_dbg_select_s cn68xxp1;
-	struct cvmx_sli_dbg_select_s cnf71xx;
-};
-
-union cvmx_sli_dmax_cnt {
-	uint64_t u64;
-	struct cvmx_sli_dmax_cnt_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-		uint64_t reserved_32_63:32;
-		uint64_t cnt:32;
-#else
-		uint64_t cnt:32;
-		uint64_t reserved_32_63:32;
-#endif
-	} s;
-	struct cvmx_sli_dmax_cnt_s cn61xx;
-	struct cvmx_sli_dmax_cnt_s cn63xx;
-	struct cvmx_sli_dmax_cnt_s cn63xxp1;
-	struct cvmx_sli_dmax_cnt_s cn66xx;
-	struct cvmx_sli_dmax_cnt_s cn68xx;
-	struct cvmx_sli_dmax_cnt_s cn68xxp1;
-	struct cvmx_sli_dmax_cnt_s cnf71xx;
-};
-
-union cvmx_sli_dmax_int_level {
-	uint64_t u64;
-	struct cvmx_sli_dmax_int_level_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-		uint64_t time:32;
-		uint64_t cnt:32;
-#else
-		uint64_t cnt:32;
-		uint64_t time:32;
-#endif
-	} s;
-	struct cvmx_sli_dmax_int_level_s cn61xx;
-	struct cvmx_sli_dmax_int_level_s cn63xx;
-	struct cvmx_sli_dmax_int_level_s cn63xxp1;
-	struct cvmx_sli_dmax_int_level_s cn66xx;
-	struct cvmx_sli_dmax_int_level_s cn68xx;
-	struct cvmx_sli_dmax_int_level_s cn68xxp1;
-	struct cvmx_sli_dmax_int_level_s cnf71xx;
-};
-
-union cvmx_sli_dmax_tim {
-	uint64_t u64;
-	struct cvmx_sli_dmax_tim_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-		uint64_t reserved_32_63:32;
-		uint64_t tim:32;
-#else
-		uint64_t tim:32;
-		uint64_t reserved_32_63:32;
-#endif
-	} s;
-	struct cvmx_sli_dmax_tim_s cn61xx;
-	struct cvmx_sli_dmax_tim_s cn63xx;
-	struct cvmx_sli_dmax_tim_s cn63xxp1;
-	struct cvmx_sli_dmax_tim_s cn66xx;
-	struct cvmx_sli_dmax_tim_s cn68xx;
-	struct cvmx_sli_dmax_tim_s cn68xxp1;
-	struct cvmx_sli_dmax_tim_s cnf71xx;
-};
-
-union cvmx_sli_int_enb_ciu {
-	uint64_t u64;
-	struct cvmx_sli_int_enb_ciu_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-		uint64_t reserved_62_63:2;
-		uint64_t pipe_err:1;
-		uint64_t ill_pad:1;
-		uint64_t sprt3_err:1;
-		uint64_t sprt2_err:1;
-		uint64_t sprt1_err:1;
-		uint64_t sprt0_err:1;
-		uint64_t pins_err:1;
-		uint64_t pop_err:1;
-		uint64_t pdi_err:1;
-		uint64_t pgl_err:1;
-		uint64_t pin_bp:1;
-		uint64_t pout_err:1;
-		uint64_t psldbof:1;
-		uint64_t pidbof:1;
-		uint64_t reserved_38_47:10;
-		uint64_t dtime:2;
-		uint64_t dcnt:2;
-		uint64_t dmafi:2;
-		uint64_t reserved_28_31:4;
-		uint64_t m3_un_wi:1;
-		uint64_t m3_un_b0:1;
-		uint64_t m3_up_wi:1;
-		uint64_t m3_up_b0:1;
-		uint64_t m2_un_wi:1;
-		uint64_t m2_un_b0:1;
-		uint64_t m2_up_wi:1;
-		uint64_t m2_up_b0:1;
-		uint64_t reserved_18_19:2;
-		uint64_t mio_int1:1;
-		uint64_t mio_int0:1;
-		uint64_t m1_un_wi:1;
-		uint64_t m1_un_b0:1;
-		uint64_t m1_up_wi:1;
-		uint64_t m1_up_b0:1;
-		uint64_t m0_un_wi:1;
-		uint64_t m0_un_b0:1;
-		uint64_t m0_up_wi:1;
-		uint64_t m0_up_b0:1;
-		uint64_t reserved_6_7:2;
-		uint64_t ptime:1;
-		uint64_t pcnt:1;
-		uint64_t iob2big:1;
-		uint64_t bar0_to:1;
-		uint64_t reserved_1_1:1;
-		uint64_t rml_to:1;
-#else
-		uint64_t rml_to:1;
-		uint64_t reserved_1_1:1;
-		uint64_t bar0_to:1;
-		uint64_t iob2big:1;
-		uint64_t pcnt:1;
-		uint64_t ptime:1;
-		uint64_t reserved_6_7:2;
-		uint64_t m0_up_b0:1;
-		uint64_t m0_up_wi:1;
-		uint64_t m0_un_b0:1;
-		uint64_t m0_un_wi:1;
-		uint64_t m1_up_b0:1;
-		uint64_t m1_up_wi:1;
-		uint64_t m1_un_b0:1;
-		uint64_t m1_un_wi:1;
-		uint64_t mio_int0:1;
-		uint64_t mio_int1:1;
-		uint64_t reserved_18_19:2;
-		uint64_t m2_up_b0:1;
-		uint64_t m2_up_wi:1;
-		uint64_t m2_un_b0:1;
-		uint64_t m2_un_wi:1;
-		uint64_t m3_up_b0:1;
-		uint64_t m3_up_wi:1;
-		uint64_t m3_un_b0:1;
-		uint64_t m3_un_wi:1;
-		uint64_t reserved_28_31:4;
-		uint64_t dmafi:2;
-		uint64_t dcnt:2;
-		uint64_t dtime:2;
-		uint64_t reserved_38_47:10;
-		uint64_t pidbof:1;
-		uint64_t psldbof:1;
-		uint64_t pout_err:1;
-		uint64_t pin_bp:1;
-		uint64_t pgl_err:1;
-		uint64_t pdi_err:1;
-		uint64_t pop_err:1;
-		uint64_t pins_err:1;
-		uint64_t sprt0_err:1;
-		uint64_t sprt1_err:1;
-		uint64_t sprt2_err:1;
-		uint64_t sprt3_err:1;
-		uint64_t ill_pad:1;
-		uint64_t pipe_err:1;
-		uint64_t reserved_62_63:2;
-#endif
-	} s;
-	struct cvmx_sli_int_enb_ciu_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-		uint64_t reserved_61_63:3;
-		uint64_t ill_pad:1;
-		uint64_t sprt3_err:1;
-		uint64_t sprt2_err:1;
-		uint64_t sprt1_err:1;
-		uint64_t sprt0_err:1;
-		uint64_t pins_err:1;
-		uint64_t pop_err:1;
-		uint64_t pdi_err:1;
-		uint64_t pgl_err:1;
-		uint64_t pin_bp:1;
-		uint64_t pout_err:1;
-		uint64_t psldbof:1;
-		uint64_t pidbof:1;
-		uint64_t reserved_38_47:10;
-		uint64_t dtime:2;
-		uint64_t dcnt:2;
-		uint64_t dmafi:2;
-		uint64_t reserved_28_31:4;
-		uint64_t m3_un_wi:1;
-		uint64_t m3_un_b0:1;
-		uint64_t m3_up_wi:1;
-		uint64_t m3_up_b0:1;
-		uint64_t m2_un_wi:1;
-		uint64_t m2_un_b0:1;
-		uint64_t m2_up_wi:1;
-		uint64_t m2_up_b0:1;
-		uint64_t reserved_18_19:2;
-		uint64_t mio_int1:1;
-		uint64_t mio_int0:1;
-		uint64_t m1_un_wi:1;
-		uint64_t m1_un_b0:1;
-		uint64_t m1_up_wi:1;
-		uint64_t m1_up_b0:1;
-		uint64_t m0_un_wi:1;
-		uint64_t m0_un_b0:1;
-		uint64_t m0_up_wi:1;
-		uint64_t m0_up_b0:1;
-		uint64_t reserved_6_7:2;
-		uint64_t ptime:1;
-		uint64_t pcnt:1;
-		uint64_t iob2big:1;
-		uint64_t bar0_to:1;
-		uint64_t reserved_1_1:1;
-		uint64_t rml_to:1;
-#else
-		uint64_t rml_to:1;
-		uint64_t reserved_1_1:1;
-		uint64_t bar0_to:1;
-		uint64_t iob2big:1;
-		uint64_t pcnt:1;
-		uint64_t ptime:1;
-		uint64_t reserved_6_7:2;
-		uint64_t m0_up_b0:1;
-		uint64_t m0_up_wi:1;
-		uint64_t m0_un_b0:1;
-		uint64_t m0_un_wi:1;
-		uint64_t m1_up_b0:1;
-		uint64_t m1_up_wi:1;
-		uint64_t m1_un_b0:1;
-		uint64_t m1_un_wi:1;
-		uint64_t mio_int0:1;
-		uint64_t mio_int1:1;
-		uint64_t reserved_18_19:2;
-		uint64_t m2_up_b0:1;
-		uint64_t m2_up_wi:1;
-		uint64_t m2_un_b0:1;
-		uint64_t m2_un_wi:1;
-		uint64_t m3_up_b0:1;
-		uint64_t m3_up_wi:1;
-		uint64_t m3_un_b0:1;
-		uint64_t m3_un_wi:1;
-		uint64_t reserved_28_31:4;
-		uint64_t dmafi:2;
-		uint64_t dcnt:2;
-		uint64_t dtime:2;
-		uint64_t reserved_38_47:10;
-		uint64_t pidbof:1;
-		uint64_t psldbof:1;
-		uint64_t pout_err:1;
-		uint64_t pin_bp:1;
-		uint64_t pgl_err:1;
-		uint64_t pdi_err:1;
-		uint64_t pop_err:1;
-		uint64_t pins_err:1;
-		uint64_t sprt0_err:1;
-		uint64_t sprt1_err:1;
-		uint64_t sprt2_err:1;
-		uint64_t sprt3_err:1;
-		uint64_t ill_pad:1;
-		uint64_t reserved_61_63:3;
-#endif
-	} cn61xx;
-	struct cvmx_sli_int_enb_ciu_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-		uint64_t reserved_61_63:3;
-		uint64_t ill_pad:1;
-		uint64_t reserved_58_59:2;
-		uint64_t sprt1_err:1;
-		uint64_t sprt0_err:1;
-		uint64_t pins_err:1;
-		uint64_t pop_err:1;
-		uint64_t pdi_err:1;
-		uint64_t pgl_err:1;
-		uint64_t pin_bp:1;
-		uint64_t pout_err:1;
-		uint64_t psldbof:1;
-		uint64_t pidbof:1;
-		uint64_t reserved_38_47:10;
-		uint64_t dtime:2;
-		uint64_t dcnt:2;
-		uint64_t dmafi:2;
-		uint64_t reserved_18_31:14;
-		uint64_t mio_int1:1;
-		uint64_t mio_int0:1;
-		uint64_t m1_un_wi:1;
-		uint64_t m1_un_b0:1;
-		uint64_t m1_up_wi:1;
-		uint64_t m1_up_b0:1;
-		uint64_t m0_un_wi:1;
-		uint64_t m0_un_b0:1;
-		uint64_t m0_up_wi:1;
-		uint64_t m0_up_b0:1;
-		uint64_t reserved_6_7:2;
-		uint64_t ptime:1;
-		uint64_t pcnt:1;
-		uint64_t iob2big:1;
-		uint64_t bar0_to:1;
-		uint64_t reserved_1_1:1;
-		uint64_t rml_to:1;
-#else
-		uint64_t rml_to:1;
-		uint64_t reserved_1_1:1;
-		uint64_t bar0_to:1;
-		uint64_t iob2big:1;
-		uint64_t pcnt:1;
-		uint64_t ptime:1;
-		uint64_t reserved_6_7:2;
-		uint64_t m0_up_b0:1;
-		uint64_t m0_up_wi:1;
-		uint64_t m0_un_b0:1;
-		uint64_t m0_un_wi:1;
-		uint64_t m1_up_b0:1;
-		uint64_t m1_up_wi:1;
-		uint64_t m1_un_b0:1;
-		uint64_t m1_un_wi:1;
-		uint64_t mio_int0:1;
-		uint64_t mio_int1:1;
-		uint64_t reserved_18_31:14;
-		uint64_t dmafi:2;
-		uint64_t dcnt:2;
-		uint64_t dtime:2;
-		uint64_t reserved_38_47:10;
-		uint64_t pidbof:1;
-		uint64_t psldbof:1;
-		uint64_t pout_err:1;
-		uint64_t pin_bp:1;
-		uint64_t pgl_err:1;
-		uint64_t pdi_err:1;
-		uint64_t pop_err:1;
-		uint64_t pins_err:1;
-		uint64_t sprt0_err:1;
-		uint64_t sprt1_err:1;
-		uint64_t reserved_58_59:2;
-		uint64_t ill_pad:1;
-		uint64_t reserved_61_63:3;
-#endif
-	} cn63xx;
-	struct cvmx_sli_int_enb_ciu_cn63xx cn63xxp1;
-	struct cvmx_sli_int_enb_ciu_cn61xx cn66xx;
-	struct cvmx_sli_int_enb_ciu_cn68xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-		uint64_t reserved_62_63:2;
-		uint64_t pipe_err:1;
-		uint64_t ill_pad:1;
-		uint64_t reserved_58_59:2;
-		uint64_t sprt1_err:1;
-		uint64_t sprt0_err:1;
-		uint64_t pins_err:1;
-		uint64_t pop_err:1;
-		uint64_t pdi_err:1;
-		uint64_t pgl_err:1;
-		uint64_t reserved_51_51:1;
-		uint64_t pout_err:1;
-		uint64_t psldbof:1;
-		uint64_t pidbof:1;
-		uint64_t reserved_38_47:10;
-		uint64_t dtime:2;
-		uint64_t dcnt:2;
-		uint64_t dmafi:2;
-		uint64_t reserved_18_31:14;
-		uint64_t mio_int1:1;
-		uint64_t mio_int0:1;
-		uint64_t m1_un_wi:1;
-		uint64_t m1_un_b0:1;
-		uint64_t m1_up_wi:1;
-		uint64_t m1_up_b0:1;
-		uint64_t m0_un_wi:1;
-		uint64_t m0_un_b0:1;
-		uint64_t m0_up_wi:1;
-		uint64_t m0_up_b0:1;
-		uint64_t reserved_6_7:2;
-		uint64_t ptime:1;
-		uint64_t pcnt:1;
-		uint64_t iob2big:1;
-		uint64_t bar0_to:1;
-		uint64_t reserved_1_1:1;
-		uint64_t rml_to:1;
-#else
-		uint64_t rml_to:1;
-		uint64_t reserved_1_1:1;
-		uint64_t bar0_to:1;
-		uint64_t iob2big:1;
-		uint64_t pcnt:1;
-		uint64_t ptime:1;
-		uint64_t reserved_6_7:2;
-		uint64_t m0_up_b0:1;
-		uint64_t m0_up_wi:1;
-		uint64_t m0_un_b0:1;
-		uint64_t m0_un_wi:1;
-		uint64_t m1_up_b0:1;
-		uint64_t m1_up_wi:1;
-		uint64_t m1_un_b0:1;
-		uint64_t m1_un_wi:1;
-		uint64_t mio_int0:1;
-		uint64_t mio_int1:1;
-		uint64_t reserved_18_31:14;
-		uint64_t dmafi:2;
-		uint64_t dcnt:2;
-		uint64_t dtime:2;
-		uint64_t reserved_38_47:10;
-		uint64_t pidbof:1;
-		uint64_t psldbof:1;
-		uint64_t pout_err:1;
-		uint64_t reserved_51_51:1;
-		uint64_t pgl_err:1;
-		uint64_t pdi_err:1;
-		uint64_t pop_err:1;
-		uint64_t pins_err:1;
-		uint64_t sprt0_err:1;
-		uint64_t sprt1_err:1;
-		uint64_t reserved_58_59:2;
-		uint64_t ill_pad:1;
-		uint64_t pipe_err:1;
-		uint64_t reserved_62_63:2;
-#endif
-	} cn68xx;
-	struct cvmx_sli_int_enb_ciu_cn68xx cn68xxp1;
-	struct cvmx_sli_int_enb_ciu_cn61xx cnf71xx;
-};
-
-union cvmx_sli_int_enb_portx {
-	uint64_t u64;
-	struct cvmx_sli_int_enb_portx_s {
-#ifdef __BIG_ENDIAN_BITFIELD
-		uint64_t reserved_62_63:2;
-		uint64_t pipe_err:1;
-		uint64_t ill_pad:1;
-		uint64_t sprt3_err:1;
-		uint64_t sprt2_err:1;
-		uint64_t sprt1_err:1;
-		uint64_t sprt0_err:1;
-		uint64_t pins_err:1;
-		uint64_t pop_err:1;
-		uint64_t pdi_err:1;
-		uint64_t pgl_err:1;
-		uint64_t pin_bp:1;
-		uint64_t pout_err:1;
-		uint64_t psldbof:1;
-		uint64_t pidbof:1;
-		uint64_t reserved_38_47:10;
-		uint64_t dtime:2;
-		uint64_t dcnt:2;
-		uint64_t dmafi:2;
-		uint64_t reserved_28_31:4;
-		uint64_t m3_un_wi:1;
-		uint64_t m3_un_b0:1;
-		uint64_t m3_up_wi:1;
-		uint64_t m3_up_b0:1;
-		uint64_t m2_un_wi:1;
-		uint64_t m2_un_b0:1;
-		uint64_t m2_up_wi:1;
-		uint64_t m2_up_b0:1;
-		uint64_t mac1_int:1;
-		uint64_t mac0_int:1;
-		uint64_t mio_int1:1;
-		uint64_t mio_int0:1;
-		uint64_t m1_un_wi:1;
-		uint64_t m1_un_b0:1;
-		uint64_t m1_up_wi:1;
-		uint64_t m1_up_b0:1;
-		uint64_t m0_un_wi:1;
-		uint64_t m0_un_b0:1;
-		uint64_t m0_up_wi:1;
-		uint64_t m0_up_b0:1;
-		uint64_t reserved_6_7:2;
-		uint64_t ptime:1;
-		uint64_t pcnt:1;
-		uint64_t iob2big:1;
-		uint64_t bar0_to:1;
-		uint64_t reserved_1_1:1;
-		uint64_t rml_to:1;
-#else
-		uint64_t rml_to:1;
-		uint64_t reserved_1_1:1;
-		uint64_t bar0_to:1;
-		uint64_t iob2big:1;
-		uint64_t pcnt:1;
-		uint64_t ptime:1;
-		uint64_t reserved_6_7:2;
-		uint64_t m0_up_b0:1;
-		uint64_t m0_up_wi:1;
-		uint64_t m0_un_b0:1;
-		uint64_t m0_un_wi:1;
-		uint64_t m1_up_b0:1;
-		uint64_t m1_up_wi:1;
-		uint64_t m1_un_b0:1;
-		uint64_t m1_un_wi:1;
-		uint64_t mio_int0:1;
-		uint64_t mio_int1:1;
-		uint64_t mac0_int:1;
-		uint64_t mac1_int:1;
-		uint64_t m2_up_b0:1;
-		uint64_t m2_up_wi:1;
-		uint64_t m2_un_b0:1;
-		uint64_t m2_un_wi:1;
-		uint64_t m3_up_b0:1;
-		uint64_t m3_up_wi:1;
-		uint64_t m3_un_b0:1;
-		uint64_t m3_un_wi:1;
-		uint64_t reserved_28_31:4;
-		uint64_t dmafi:2;
-		uint64_t dcnt:2;
-		uint64_t dtime:2;
-		uint64_t reserved_38_47:10;
-		uint64_t pidbof:1;
-		uint64_t psldbof:1;
-		uint64_t pout_err:1;
-		uint64_t pin_bp:1;
-		uint64_t pgl_err:1;
-		uint64_t pdi_err:1;
-		uint64_t pop_err:1;
-		uint64_t pins_err:1;
-		uint64_t sprt0_err:1;
-		uint64_t sprt1_err:1;
-		uint64_t sprt2_err:1;
-		uint64_t sprt3_err:1;
-		uint64_t ill_pad:1;
-		uint64_t pipe_err:1;
-		uint64_t reserved_62_63:2;
-#endif
-	} s;
-	struct cvmx_sli_int_enb_portx_cn61xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-		uint64_t reserved_61_63:3;
-		uint64_t ill_pad:1;
-		uint64_t sprt3_err:1;
-		uint64_t sprt2_err:1;
-		uint64_t sprt1_err:1;
-		uint64_t sprt0_err:1;
-		uint64_t pins_err:1;
-		uint64_t pop_err:1;
-		uint64_t pdi_err:1;
-		uint64_t pgl_err:1;
-		uint64_t pin_bp:1;
-		uint64_t pout_err:1;
-		uint64_t psldbof:1;
-		uint64_t pidbof:1;
-		uint64_t reserved_38_47:10;
-		uint64_t dtime:2;
-		uint64_t dcnt:2;
-		uint64_t dmafi:2;
-		uint64_t reserved_28_31:4;
-		uint64_t m3_un_wi:1;
-		uint64_t m3_un_b0:1;
-		uint64_t m3_up_wi:1;
-		uint64_t m3_up_b0:1;
-		uint64_t m2_un_wi:1;
-		uint64_t m2_un_b0:1;
-		uint64_t m2_up_wi:1;
-		uint64_t m2_up_b0:1;
-		uint64_t mac1_int:1;
-		uint64_t mac0_int:1;
-		uint64_t mio_int1:1;
-		uint64_t mio_int0:1;
-		uint64_t m1_un_wi:1;
-		uint64_t m1_un_b0:1;
-		uint64_t m1_up_wi:1;
-		uint64_t m1_up_b0:1;
-		uint64_t m0_un_wi:1;
-		uint64_t m0_un_b0:1;
-		uint64_t m0_up_wi:1;
-		uint64_t m0_up_b0:1;
-		uint64_t reserved_6_7:2;
-		uint64_t ptime:1;
-		uint64_t pcnt:1;
-		uint64_t iob2big:1;
-		uint64_t bar0_to:1;
-		uint64_t reserved_1_1:1;
-		uint64_t rml_to:1;
-#else
-		uint64_t rml_to:1;
-		uint64_t reserved_1_1:1;
-		uint64_t bar0_to:1;
-		uint64_t iob2big:1;
-		uint64_t pcnt:1;
-		uint64_t ptime:1;
-		uint64_t reserved_6_7:2;
-		uint64_t m0_up_b0:1;
-		uint64_t m0_up_wi:1;
-		uint64_t m0_un_b0:1;
-		uint64_t m0_un_wi:1;
-		uint64_t m1_up_b0:1;
-		uint64_t m1_up_wi:1;
-		uint64_t m1_un_b0:1;
-		uint64_t m1_un_wi:1;
-		uint64_t mio_int0:1;
-		uint64_t mio_int1:1;
-		uint64_t mac0_int:1;
-		uint64_t mac1_int:1;
-		uint64_t m2_up_b0:1;
-		uint64_t m2_up_wi:1;
-		uint64_t m2_un_b0:1;
-		uint64_t m2_un_wi:1;
-		uint64_t m3_up_b0:1;
-		uint64_t m3_up_wi:1;
-		uint64_t m3_un_b0:1;
-		uint64_t m3_un_wi:1;
-		uint64_t reserved_28_31:4;
-		uint64_t dmafi:2;
-		uint64_t dcnt:2;
-		uint64_t dtime:2;
-		uint64_t reserved_38_47:10;
-		uint64_t pidbof:1;
-		uint64_t psldbof:1;
-		uint64_t pout_err:1;
-		uint64_t pin_bp:1;
-		uint64_t pgl_err:1;
-		uint64_t pdi_err:1;
-		uint64_t pop_err:1;
-		uint64_t pins_err:1;
-		uint64_t sprt0_err:1;
-		uint64_t sprt1_err:1;
-		uint64_t sprt2_err:1;
-		uint64_t sprt3_err:1;
-		uint64_t ill_pad:1;
-		uint64_t reserved_61_63:3;
-#endif
-	} cn61xx;
-	struct cvmx_sli_int_enb_portx_cn63xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-		uint64_t reserved_61_63:3;
-		uint64_t ill_pad:1;
-		uint64_t reserved_58_59:2;
-		uint64_t sprt1_err:1;
-		uint64_t sprt0_err:1;
-		uint64_t pins_err:1;
-		uint64_t pop_err:1;
-		uint64_t pdi_err:1;
-		uint64_t pgl_err:1;
-		uint64_t pin_bp:1;
-		uint64_t pout_err:1;
-		uint64_t psldbof:1;
-		uint64_t pidbof:1;
-		uint64_t reserved_38_47:10;
-		uint64_t dtime:2;
-		uint64_t dcnt:2;
-		uint64_t dmafi:2;
-		uint64_t reserved_20_31:12;
-		uint64_t mac1_int:1;
-		uint64_t mac0_int:1;
-		uint64_t mio_int1:1;
-		uint64_t mio_int0:1;
-		uint64_t m1_un_wi:1;
-		uint64_t m1_un_b0:1;
-		uint64_t m1_up_wi:1;
-		uint64_t m1_up_b0:1;
-		uint64_t m0_un_wi:1;
-		uint64_t m0_un_b0:1;
-		uint64_t m0_up_wi:1;
-		uint64_t m0_up_b0:1;
-		uint64_t reserved_6_7:2;
-		uint64_t ptime:1;
-		uint64_t pcnt:1;
-		uint64_t iob2big:1;
-		uint64_t bar0_to:1;
-		uint64_t reserved_1_1:1;
-		uint64_t rml_to:1;
-#else
-		uint64_t rml_to:1;
-		uint64_t reserved_1_1:1;
-		uint64_t bar0_to:1;
-		uint64_t iob2big:1;
-		uint64_t pcnt:1;
-		uint64_t ptime:1;
-		uint64_t reserved_6_7:2;
-		uint64_t m0_up_b0:1;
-		uint64_t m0_up_wi:1;
-		uint64_t m0_un_b0:1;
-		uint64_t m0_un_wi:1;
-		uint64_t m1_up_b0:1;
-		uint64_t m1_up_wi:1;
-		uint64_t m1_un_b0:1;
-		uint64_t m1_un_wi:1;
-		uint64_t mio_int0:1;
-		uint64_t mio_int1:1;
-		uint64_t mac0_int:1;
-		uint64_t mac1_int:1;
-		uint64_t reserved_20_31:12;
-		uint64_t dmafi:2;
-		uint64_t dcnt:2;
-		uint64_t dtime:2;
-		uint64_t reserved_38_47:10;
-		uint64_t pidbof:1;
-		uint64_t psldbof:1;
-		uint64_t pout_err:1;
-		uint64_t pin_bp:1;
-		uint64_t pgl_err:1;
-		uint64_t pdi_err:1;
-		uint64_t pop_err:1;
-		uint64_t pins_err:1;
-		uint64_t sprt0_err:1;
-		uint64_t sprt1_err:1;
-		uint64_t reserved_58_59:2;
-		uint64_t ill_pad:1;
-		uint64_t reserved_61_63:3;
-#endif
-	} cn63xx;
-	struct cvmx_sli_int_enb_portx_cn63xx cn63xxp1;
-	struct cvmx_sli_int_enb_portx_cn61xx cn66xx;
-	struct cvmx_sli_int_enb_portx_cn68xx {
-#ifdef __BIG_ENDIAN_BITFIELD
-		uint64_t reserved_62_63:2;
-		uint64_t pipe_err:1;
-		uint64_t ill_pad:1;
-		uint64_t reserved_58_59:2;
-		uint64_t sprt1_err:1;
-		uint64_t sprt0_err:1;
-		uint64_t pins_err:1;
-		uint64_t pop_err:1;
-		uint64_t pdi_err:1;
-		uint64_t pgl_err:1;
-		uint64_t reserved_51_51:1;
-		uint64_t pout_err:1;
-		uint64_t psldbof:1;
-		uint64_t pidbof:1;
-		uint64_t reserved_38_47:10;
-		uint64_t dtime:2;
-		uint64_t dcnt:2;
-		uint64_t dmafi:2;
-		uint64_t reserved_20_31:12;
-		uint64_t mac1_int:1;
-		uint64_t mac0_int:1;
-		uint64_t mio_int1:1;
-		uint64_t mio_int0:1;
-		uint64_t m1_un_wi:1;
-		uint64_t m1_un_b0:1;
-		uint64_t m1_up_wi:1;
-		uint64_t m1_up_b0:1;
-		uint64_t m0_un_wi:1;
-		uint64_t m0_un_b0:1;