diff options
author | Sergio Paracuellos <sergio.paracuellos@gmail.com> | 2018-08-03 10:27:06 +0200 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2018-08-08 14:08:41 +0200 |
commit | 8594351af0f9e065885a6bbcb5248736e8a5612a (patch) | |
tree | 0dcda6d08efd9f15cc7cee4fd639cdea6b4450a3 | |
parent | 88e8fa0c26ba400ac15fad9cf6461f746ddb3aca (diff) |
staging: mt7621-pci: rename RALINK_PCI_CONFIG_DATA_VIRTUAL_REG definition
RALINK_PCI_CONFIG_DATA_VIRTUAL_REG is a very long name. Make it a bit
shorter renaming it to RALINK_PCI_CONFIG_DATA.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Tested-by: NeilBrown <neil@brown.name>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r-- | drivers/staging/mt7621-pci/pci-mt7621.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c index c288b26db16d..dd1a72890caf 100644 --- a/drivers/staging/mt7621-pci/pci-mt7621.c +++ b/drivers/staging/mt7621-pci/pci-mt7621.c @@ -67,7 +67,7 @@ #define RALINK_PCIE2_CLK_EN BIT(26) #define RALINK_PCI_CONFIG_ADDR 0x20 -#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24 +#define RALINK_PCI_CONFIG_DATA 0x24 #define RALINK_PCI_MEMBASE 0x28 #define RALINK_PCI_IOBASE 0x2C #define RALINK_PCIE0_RST BIT(24) @@ -187,7 +187,7 @@ static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus, writel(address, pcie->base + RALINK_PCI_CONFIG_ADDR); - return pcie->base + RALINK_PCI_CONFIG_DATA_VIRTUAL_REG + (where & 3); + return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3); } struct pci_ops mt7621_pci_ops = { @@ -202,7 +202,7 @@ read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg) u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg); pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR); - return pcie_read(pcie, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG); + return pcie_read(pcie, RALINK_PCI_CONFIG_DATA); } static void @@ -211,7 +211,7 @@ write_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg, u32 val) u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg); pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR); - pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG); + pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA); } int |