[AMD][F17h] CCD_AMD_Family_17h_Temp as a function pointer to capable processors1.80-rc.1

BankGroupSwap: SMU registers dump ; BIOS logic documented

3 files changed, 42 insertions, 1 deletions

diff --git a/amdmsr.h b/amdmsr.h
index 16d26c6..4b1a470 100644
--- a/amdmsr.h
+++ b/amdmsr.h
@@ -849,6 +849,32 @@ typedef union
 	#define SMU_AMD_UMC_BASE_CHA_F17H(_cha)	(0x00050000 + (_cha << 20))
 #endif
 
+/*
+TODO(BankGroupSwap)
+
+BGS[ON]
+zencli smu 0x50058
+0xcba65321 (3416675105) 	11001011101001100101001100100001
+
+BGS[OFF][AUTO]
+zencli smu 0x50058
+0x87654321 (2271560481) 	10000111011001010100001100100001
+*/
+
+/*
+TODO(BankGroupSwap Alternate)
+
+BGS_Alt[ON][AUTO]
+zencli smu 0x500D0
+0x111107f1 (286328817
+
+BGS_Alt[OFF]
+zencli smu 0x500D0
+0x11110001 (286326785)
+
+Remark: if BGS_Alt[ON][AUTO] set then BGS[OFF]
+*/
+
 typedef union
 {	/* SMU: address = 0x50080					*/
 	unsigned int		value;
diff --git a/corefreqk.c b/corefreqk.c
index f5761f2..81ff63f 100644
--- a/corefreqk.c
+++ b/corefreqk.c
@@ -5205,6 +5205,15 @@ void Query_AMD_Family_17h(unsigned int cpu)
     }
 	Default_Unlock_Reset();
 
+	switch (PUBLIC(RO(Proc))->ArchID) {
+	case AMD_EPYC_Rome:
+	case AMD_Zen2_CPK:
+	case AMD_Zen2_APU:
+	case AMD_Zen2_MTS:
+		CCD_AMD_Family_17h_Temp = CCD_AMD_Family_17h_Zen2_Temp;
+		break;
+	}
+
 	if (Compute_AMD_Zen_Boost(cpu) == true)
 	{	/*	Count the Xtra Boost ratios			*/
 		PUBLIC(RO(Proc))->Features.TDP_Levels = 2;
@@ -8580,7 +8589,7 @@ void Pkg_AMD_Family_17h_Temp(CORE_RO *Core, unsigned int SMN_Address)
 	}
 }
 
-void CCD_AMD_Family_17h_Temp(CORE_RO *Core, unsigned int SMN_Address)
+void CCD_AMD_Family_17h_Zen2_Temp(CORE_RO *Core, unsigned int SMN_Address)
 {
 	TCCD_REGISTER TccdSensor = {.value = 0};
 
diff --git a/corefreqk.h b/corefreqk.h
index cb4a603..7ab87e7 100644
--- a/corefreqk.h
+++ b/corefreqk.h
@@ -1031,6 +1031,12 @@ static void Start_AMD_Family_17h(void *arg) ;
 static void Stop_AMD_Family_17h(void *arg) ;
 extern void InitTimer_AMD_Family_17h(unsigned int cpu) ;
 
+void Core_AMD_F17h_No_Sensor(CORE_RO *Core, unsigned int SMN_Address)
+{
+}
+void CCD_AMD_Family_17h_Zen2_Temp(CORE_RO *Core, unsigned int SMN_Address) ;
+void (*CCD_AMD_Family_17h_Temp)(CORE_RO*, unsigned int)=Core_AMD_F17h_No_Sensor;
+
 /*	[Void]								*/
 #define _Void_Signature {.ExtFamily=0x0, .Family=0x0, .ExtModel=0x0, .Model=0x0}