sparcv9cap.c: reiterate CPU detection logic [from HEAD].

2 files changed, 66 insertions, 18 deletions

diff --git a/crypto/sparccpuid.S b/crypto/sparccpuid.S
index e53c7fad61..1e0756a173 100644
--- a/crypto/sparccpuid.S
+++ b/crypto/sparccpuid.S
@@ -232,13 +232,59 @@ _sparcv9_rdtick:
 .type	_sparcv9_rdtick,#function
 .size	_sparcv9_rdtick,.-_sparcv9_rdtick
 
+! Probe and instrument VIS1 instruction. Output is number of cycles it
+! takes to execute rdtick and pair of VIS1 instructions. US-Tx VIS unit
+! is slow (documented to be 6 cycles on T2) and the core is in-order
+! single-issue, it should be possible to distinguish Tx reliably...
+! Observed return values are:
+!
+!	UltraSPARC IIi		7
+!	UltraSPARC III		7
+!	UltraSPARC T1		24
+!
+! Numbers for T2 and SPARC64 V-VII are more than welcomed.
+!
+! It would be possible to detect specifically US-T1 by instrumenting
+! fmul8ulx16, which is emulated on T1 and as such accounts for quite
+! a lot of %tick-s, couple of thousand on Linux...
 .global	_sparcv9_vis1_probe
 .align	8
 _sparcv9_vis1_probe:
-	.word	0x81b00c20	!fzeros	%f0
-	add	%sp,BIAS+2,%o0
+	.word	0x91410000	!rd	%tick,%o0
+	.word	0x81b00d80	!fxor	%f0,%f0,%f0
+	.word	0x85b08d82	!fxor	%f2,%f2,%f2
+	.word	0x93410000	!rd	%tick,%o1
+	.word	0x81b00d80	!fxor	%f0,%f0,%f0
+	.word	0x85b08d82	!fxor	%f2,%f2,%f2
+	.word	0x95410000	!rd	%tick,%o2
+	.word	0x81b00d80	!fxor	%f0,%f0,%f0
+	.word	0x85b08d82	!fxor	%f2,%f2,%f2
+	.word	0x97410000	!rd	%tick,%o3
+	.word	0x81b00d80	!fxor	%f0,%f0,%f0
+	.word	0x85b08d82	!fxor	%f2,%f2,%f2
+	.word	0x99410000	!rd	%tick,%o4
+
+	! calculate intervals
+	sub	%o1,%o0,%o0
+	sub	%o2,%o1,%o1
+	sub	%o3,%o2,%o2
+	sub	%o4,%o3,%o3
+
+	! find minumum value
+	cmp	%o0,%o1
+	.word	0x38680002	!bgu,a	%xcc,.+8
+	mov	%o1,%o0
+	cmp	%o0,%o2
+	.word	0x38680002	!bgu,a	%xcc,.+8
+	mov	%o2,%o0
+	cmp	%o0,%o3
+	.word	0x38680002	!bgu,a	%xcc,.+8
+	mov	%o3,%o0
+
+	! check for ASI_FP16_P is redundant...
+	add	%sp,BIAS+2,%o1
 	retl
-	.word	0xc19a1a40	!ldda	[%o0]ASI_FP16_P,%f0
+	.word	0xc19a5a40	!ldda	[%o1]ASI_FP16_P,%f0
 .type	_sparcv9_vis1_probe,#function
 .size	_sparcv9_vis1_probe,.-_sparcv9_vis1_probe
 
diff --git a/crypto/sparcv9cap.c b/crypto/sparcv9cap.c
index 6308036250..bb0c8e73a9 100644
--- a/crypto/sparcv9cap.c
+++ b/crypto/sparcv9cap.c
@@ -27,7 +27,7 @@ int bn_mul_mont(BN_ULONG *rp, const BN_ULONG *ap, const BN_ULONG *bp, const BN_U
 	}
 
 unsigned long	_sparcv9_rdtick(void);
-void		_sparcv9_vis1_probe(void);
+unsigned long	_sparcv9_vis1_probe(void);
 
 unsigned long OPENSSL_rdtsc(void)
 	{
@@ -176,33 +176,35 @@ void OPENSSL_cpuid_setup(void)
 	common_act.sa_mask    = all_masked;
 
 	sigaction(SIGILL,&common_act,&ill_oact);
-	sigaction(SIGBUS,&common_act,&bus_oact);/* T1 fails 16-bit ldda */
-	if ((sig=sigsetjmp(common_jmp,0)) == 0)
-		{
-		_sparcv9_vis1_probe();
-		OPENSSL_sparcv9cap_P |= SPARCV9_VIS1;
-		}
-	else if (sig == SIGBUS)			/* T1 fails 16-bit ldda */
+	if (sigsetjmp(common_jmp,0) == 0)
 		{
-		OPENSSL_sparcv9cap_P &= ~SPARCV9_PREFER_FPU;
+		_sparcv9_rdtick();
+		OPENSSL_sparcv9cap_P &= ~SPARCV9_TICK_PRIVILEGED;
 		}
 	else
 		{
-		OPENSSL_sparcv9cap_P &= ~SPARCV9_VIS1;
+		/* This happens on US-I&II, which have working VIS1
+		 * and fast FPU... In other words we are done... */
+		OPENSSL_sparcv9cap_P |= SPARCV9_TICK_PRIVILEGED;
+		sigaction(SIGILL,&ill_oact,NULL);
+		sigprocmask(SIG_SETMASK,&oset,NULL);
+		return;
 		}
-	sigaction(SIGBUS,&bus_oact,NULL);
 	sigaction(SIGILL,&ill_oact,NULL);
 
 	sigaction(SIGILL,&common_act,&ill_oact);
-	if (sigsetjmp(common_jmp,0) == 0)
+	sigaction(SIGBUS,&common_act,&bus_oact);/* T1 fails 16-bit ldda */
+	if ((sig=sigsetjmp(common_jmp,0)) == 0)
 		{
-		_sparcv9_rdtick();
-		OPENSSL_sparcv9cap_P &= ~SPARCV9_TICK_PRIVILEGED;
+		/* see sparccpud.S for details... */
+		if (_sparcv9_vis1_probe() >= 12)
+			OPENSSL_sparcv9cap_P &= ~SPARCV9_VIS1;
 		}
 	else
 		{
-		OPENSSL_sparcv9cap_P |= SPARCV9_TICK_PRIVILEGED;
+		OPENSSL_sparcv9cap_P &= ~SPARCV9_VIS1;
 		}
+	sigaction(SIGBUS,&bus_oact,NULL);
 	sigaction(SIGILL,&ill_oact,NULL);
 
 	sigprocmask(SIG_SETMASK,&oset,NULL);