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| author | Hongren Zheng <i@zenithal.me> | 2024-04-26 06:03:43 +0000 |
|---|---|---|
| committer | Tomas Mraz <tomas@openssl.org> | 2024-05-10 17:03:14 +0200 |
| commit | 8702320db98d1346c230aff1282ade3ecdca681a (patch) | |
| tree | 2615f9bc59ff6615cbc7d03081880207ca18ae2a | |
| parent | d03e5faf1892410e5697094a9806cbc8cb87b9cc (diff) | |
Implement riscv_vlen_asm for riscv32
riscvcap.c: undefined reference to 'riscv_vlen_asm'
Reviewed-by: Paul Dale <ppzgs1@gmail.com>
Reviewed-by: Tomas Mraz <tomas@openssl.org>
(Merged from https://github.com/openssl/openssl/pull/24270)
(cherry picked from commit 87314d24c4f025df1ebf47dc527cc8a96bef354a)
| -rw-r--r-- | crypto/riscv32cpuid.pl | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/crypto/riscv32cpuid.pl b/crypto/riscv32cpuid.pl index 20694e7de7..ac1c043ec9 100644 --- a/crypto/riscv32cpuid.pl +++ b/crypto/riscv32cpuid.pl @@ -84,5 +84,22 @@ OPENSSL_cleanse: ___ } +{ +my ($ret) = ('a0'); +$code .= <<___; +################################################################################ +# size_t riscv_vlen_asm(void) +# Return VLEN (i.e. the length of a vector register in bits). +.p2align 3 +.globl riscv_vlen_asm +.type riscv_vlen_asm,\@function +riscv_vlen_asm: + csrr $ret, vlenb + slli $ret, $ret, 3 + ret +.size riscv_vlen_asm,.-riscv_vlen_asm +___ +} + print $code; close STDOUT or die "error closing STDOUT: $!"; |