diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2020-12-09 11:12:31 +0100 |
|---|---|---|
| committer | Rob Herring <robh@kernel.org> | 2020-12-10 21:28:44 -0600 |
| commit | f3c6c120614cfb02827ee7bbe6c4240847cc5f12 (patch) | |
| tree | 721acaa499371b5c79f37aff940640b620e7fc95 | |
| parent | b407771668334c3268d5320217ca2b46055c5232 (diff) | |
dt-bindings: pci: rcar-pci-ep: Document missing interrupts property
The R-Car PCIe controller does not use interrupts when configured
for endpoint mode, hence the bindings do not document the interrupts
property. However, all DTS files provide interrupts properties, and
thus fail to validate.
Fix this by documenting the interrupts property.
Fixes: 4c0f80920923f103 ("dt-bindings: PCI: rcar: Add bindings for R-Car PCIe endpoint controller")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20201209101231.2206479-1-geert+renesas@glider.be
Signed-off-by: Rob Herring <robh@kernel.org>
| -rw-r--r-- | Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml index 84eeb7fe6e01..295840cf612f 100644 --- a/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml @@ -32,6 +32,10 @@ properties: - const: memory2 - const: memory3 + interrupts: + minItems: 3 + maxItems: 3 + power-domains: maxItems: 1 @@ -53,6 +57,7 @@ required: - compatible - reg - reg-names + - interrupts - resets - power-domains - clocks @@ -64,6 +69,7 @@ additionalProperties: false examples: - | #include <dt-bindings/clock/r8a774c0-cpg-mssr.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/r8a774c0-sysc.h> pcie0_ep: pcie-ep@fe000000 { @@ -75,6 +81,9 @@ examples: <0x30000000 0x8000000>, <0x38000000 0x8000000>; reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; resets = <&cpg 319>; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; clocks = <&cpg CPG_MOD 319>; |