diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-12-12 19:50:36 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2019-04-02 09:57:55 +0200 |
| commit | efca8da0c5fcc7f5617bab769faa595f7efdc593 (patch) | |
| tree | ffc46103917cdcd8733992376567ecf34d97839d | |
| parent | 01ff33a3ea57a7abf486e48a8d4d62435964038c (diff) | |
pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro
Currently the PINMUX_CFG_REG() macro must be followed by initialization
data, specifying all enum IDs. Hence the macro itself does not know
anything about the enum IDs, preventing the macro from performing any
validation on it.
Make the macro accept the enum IDs as a parameter, and update all users.
Note that array data enclosed by curly braces cannot be passed to a
macro as a parameter, hence the enum IDs are wrapped using a new macro
GROUPS().
No functional changes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
32 files changed, 1137 insertions, 1128 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-emev2.c b/drivers/pinctrl/sh-pfc/pfc-emev2.c index 310c6f3ee7cc..44192eaa97d7 100644 --- a/drivers/pinctrl/sh-pfc/pfc-emev2.c +++ b/drivers/pinctrl/sh-pfc/pfc-emev2.c @@ -1433,7 +1433,7 @@ static const struct sh_pfc_function pinmux_functions[] = { }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { - { PINMUX_CFG_REG("GPSR0", 0xe0140200, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xe0140200, 32, 1, GROUP( 0, PORT31_FN, /* PIN: J18 */ 0, PORT30_FN, /* PIN: H18 */ 0, PORT29_FN, /* PIN: G18 */ @@ -1466,9 +1466,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_JT_SEL, PORT2_FN, /* PIN: V9 */ 0, PORT1_FN, /* PIN: U10 */ 0, PORT0_FN, /* PIN: V10 */ - } + )) }, - { PINMUX_CFG_REG("GPSR1", 0xe0140204, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xe0140204, 32, 1, GROUP( FN_SDI1_CMD, PORT63_FN, /* PIN: AC21 */ FN_SDI1_CKI, PORT62_FN, /* PIN: AA23 */ FN_SDI1_CKO, PORT61_FN, /* PIN: AB22 */ @@ -1501,9 +1501,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_LCD3_R2, PORT34_FN, /* PIN: A19 */ FN_LCD3_R1, PORT33_FN, /* PIN: B20 */ FN_LCD3_R0, PORT32_FN, /* PIN: A20 */ - } + )) }, - { PINMUX_CFG_REG("GPSR2", 0xe0140208, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xe0140208, 32, 1, GROUP( FN_AB_1_0_PORT95, PORT95_FN, /* PIN: L21 */ FN_AB_1_0_PORT94, PORT94_FN, /* PIN: K21 */ FN_AB_1_0_PORT93, PORT93_FN, /* PIN: J21 */ @@ -1536,9 +1536,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SDI1_DATA2, PORT66_FN, /* PIN: AB19 */ FN_SDI1_DATA1, PORT65_FN, /* PIN: AB20 */ FN_SDI1_DATA0, PORT64_FN, /* PIN: AB21 */ - } + )) }, - { PINMUX_CFG_REG("GPSR3", 0xe014020c, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xe014020c, 32, 1, GROUP( FN_NTSC_DATA4, PORT127_FN, /* PIN: T20 */ FN_NTSC_DATA3, PORT126_FN, /* PIN: R18 */ FN_NTSC_DATA2, PORT125_FN, /* PIN: R20 */ @@ -1571,9 +1571,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_AB_9_8_PORT98, PORT98_FN, /* PIN: M20 */ FN_AB_9_8_PORT97, PORT97_FN, /* PIN: N21 */ FN_AB_A20, PORT96_FN, /* PIN: M21 */ - } + )) }, - { PINMUX_CFG_REG("GPSR4", 0xe0140210, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xe0140210, 32, 1, GROUP( 0, 0, FN_UART_1_0_PORT158, PORT158_FN, /* PIN: AB10 */ FN_UART_1_0_PORT157, PORT157_FN, /* PIN: AA10 */ @@ -1606,7 +1606,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_NTSC_DATA7, PORT130_FN, /* PIN: U18 */ FN_NTSC_DATA6, PORT129_FN, /* PIN: U20 */ FN_NTSC_DATA5, PORT128_FN, /* PIN: T18 */ - } + )) }, { PINMUX_CFG_REG_VAR("CHG_PINSEL_LCD3", 0xe0140284, 32, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c index 5acbacb3727f..f07b33c614db 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c @@ -2284,7 +2284,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { PORTCR(328, 0xe6053148), PORTCR(329, 0xe6053149), - { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) { + { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1, GROUP( MSEL1CR_31_0, MSEL1CR_31_1, 0, 0, 0, 0, @@ -2317,9 +2317,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MSEL1CR_02_0, MSEL1CR_02_1, MSEL1CR_01_0, MSEL1CR_01_1, MSEL1CR_00_0, MSEL1CR_00_1, - } + )) }, - { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) { + { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1, GROUP( MSEL3CR_31_0, MSEL3CR_31_1, 0, 0, 0, 0, @@ -2352,9 +2352,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, MSEL3CR_01_0, MSEL3CR_01_1, MSEL3CR_00_0, MSEL3CR_00_1, - } + )) }, - { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) { + { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1, GROUP( 0, 0, MSEL4CR_30_0, MSEL4CR_30_1, MSEL4CR_29_0, MSEL4CR_29_1, @@ -2387,9 +2387,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, MSEL4CR_01_0, MSEL4CR_01_1, 0, 0, - } + )) }, - { PINMUX_CFG_REG("MSEL5CR", 0xe6058028, 32, 1) { + { PINMUX_CFG_REG("MSEL5CR", 0xe6058028, 32, 1, GROUP( MSEL5CR_31_0, MSEL5CR_31_1, MSEL5CR_30_0, MSEL5CR_30_1, MSEL5CR_29_0, MSEL5CR_29_1, @@ -2422,9 +2422,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, - } + )) }, - { PINMUX_CFG_REG("MSEL8CR", 0xe6058034, 32, 1) { + { PINMUX_CFG_REG("MSEL8CR", 0xe6058034, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2457,7 +2457,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, MSEL8CR_01_0, MSEL8CR_01_1, MSEL8CR_00_0, MSEL8CR_00_1, - } + )) }, { }, }; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c index 6d761e62c6c8..d04428dbcb7a 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c @@ -3436,7 +3436,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { PORTCR(210, 0xe60530d2), /* PORT210CR */ PORTCR(211, 0xe60530d3), /* PORT211CR */ - { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) { + { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1, GROUP( MSEL1CR_31_0, MSEL1CR_31_1, MSEL1CR_30_0, MSEL1CR_30_1, MSEL1CR_29_0, MSEL1CR_29_1, @@ -3461,9 +3461,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MSEL1CR_2_0, MSEL1CR_2_1, 0, 0, MSEL1CR_0_0, MSEL1CR_0_1, - } + )) }, - { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) { + { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -3474,9 +3474,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MSEL3CR_6_0, MSEL3CR_6_1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - } + )) }, - { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) { + { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -3493,9 +3493,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, MSEL4CR_1_0, MSEL4CR_1_1, 0, 0, - } + )) }, - { PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1) { + { PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1, GROUP( MSEL5CR_31_0, MSEL5CR_31_1, MSEL5CR_30_0, MSEL5CR_30_1, MSEL5CR_29_0, MSEL5CR_29_1, @@ -3528,7 +3528,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MSEL5CR_2_0, MSEL5CR_2_1, 0, 0, MSEL5CR_0_0, MSEL5CR_0_1, - } + )) }, { }, }; diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c index 83772abffaf8..76f7c73b85b6 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77470.c @@ -2541,7 +2541,7 @@ static const struct sh_pfc_function pinmux_functions[] = { }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { - { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2573,9 +2573,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_3_FN, FN_USB1_OVC, GP_0_2_FN, FN_USB1_PWEN, GP_0_1_FN, FN_USB0_OVC, - GP_0_0_FN, FN_USB0_PWEN, } + GP_0_0_FN, FN_USB0_PWEN, )) }, - { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2607,9 +2607,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_3_FN, FN_IP1_23_20, GP_1_2_FN, FN_IP1_19_16, GP_1_1_FN, FN_IP1_15_12, - GP_1_0_FN, FN_IP1_11_8, } + GP_1_0_FN, FN_IP1_11_8, )) }, - { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP( GP_2_31_FN, FN_IP8_3_0, GP_2_30_FN, FN_IP7_31_28, GP_2_29_FN, FN_IP7_27_24, @@ -2641,9 +2641,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_3_FN, FN_IP4_19_16, GP_2_2_FN, FN_IP4_15_12, GP_2_1_FN, FN_IP4_11_8, - GP_2_0_FN, FN_IP4_7_4, } + GP_2_0_FN, FN_IP4_7_4, )) }, - { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP( 0, 0, 0, 0, GP_3_29_FN, FN_IP10_19_16, @@ -2675,9 +2675,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_3_FN, FN_IP8_19_16, GP_3_2_FN, FN_IP8_15_12, GP_3_1_FN, FN_IP8_11_8, - GP_3_0_FN, FN_IP8_7_4, } + GP_3_0_FN, FN_IP8_7_4, )) }, - { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2709,9 +2709,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_3_FN, FN_IP11_3_0, GP_4_2_FN, FN_IP10_31_28, GP_4_1_FN, FN_IP10_27_24, - GP_4_0_FN, FN_IP10_23_20, } + GP_4_0_FN, FN_IP10_23_20, )) }, - { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { + { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP( GP_5_31_FN, FN_IP17_27_24, GP_5_30_FN, FN_IP17_23_20, GP_5_29_FN, FN_IP17_19_16, @@ -2743,7 +2743,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_3_FN, FN_IP14_11_8, GP_5_2_FN, FN_IP14_7_4, GP_5_1_FN, FN_IP14_3_0, - GP_5_0_FN, FN_IP13_31_28, } + GP_5_0_FN, FN_IP13_31_28, )) }, { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32, 4, 4, 4, 4, 4, 4, 4, 4) { diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c index 068b5e6334d1..3e11686e2d6e 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c @@ -2104,7 +2104,7 @@ static const struct sh_pfc_function pinmux_functions[] = { }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { - { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1, GROUP( GP_0_31_FN, FN_IP1_14_11, GP_0_30_FN, FN_IP1_10_8, GP_0_29_FN, FN_IP1_7_5, @@ -2136,9 +2136,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_3_FN, FN_IP0_4_2, GP_0_2_FN, FN_PENC1, GP_0_1_FN, FN_PENC0, - GP_0_0_FN, FN_IP0_1_0 } + GP_0_0_FN, FN_IP0_1_0 )) }, - { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1, GROUP( GP_1_31_FN, FN_IP4_6_4, GP_1_30_FN, FN_IP4_3_1, GP_1_29_FN, FN_IP4_0, @@ -2170,9 +2170,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_3_FN, FN_IP1_27_25, GP_1_2_FN, FN_IP1_24, GP_1_1_FN, FN_WE0, - GP_1_0_FN, FN_IP1_23_21 } + GP_1_0_FN, FN_IP1_23_21 )) }, - { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1, GROUP( GP_2_31_FN, FN_IP6_7, GP_2_30_FN, FN_IP6_6_5, GP_2_29_FN, FN_IP6_4_2, @@ -2204,9 +2204,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_3_FN, FN_IP4_12_11, GP_2_2_FN, FN_IP4_10_9, GP_2_1_FN, FN_IP4_8, - GP_2_0_FN, FN_IP4_7 } + GP_2_0_FN, FN_IP4_7 )) }, - { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1, GROUP( GP_3_31_FN, FN_IP8_10_9, GP_3_30_FN, FN_IP8_8_6, GP_3_29_FN, FN_IP8_5_3, @@ -2238,9 +2238,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_3_FN, FN_IP6_10, GP_3_2_FN, FN_SSI_SCK34, GP_3_1_FN, FN_IP6_9, - GP_3_0_FN, FN_IP6_8 } + GP_3_0_FN, FN_IP6_8 )) }, - { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2272,7 +2272,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_3_FN, FN_IP8_21_19, GP_4_2_FN, FN_IP8_18_16, GP_4_1_FN, FN_IP8_15_14, - GP_4_0_FN, FN_IP8_13_11 } + GP_4_0_FN, FN_IP8_13_11 )) }, { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32, diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c index eb2f1d12b68b..4a2c16e9219c 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c @@ -3154,7 +3154,7 @@ static const struct sh_pfc_function pinmux_functions[] = { }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { - { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1, GROUP( GP_0_31_FN, FN_IP3_31_29, GP_0_30_FN, FN_IP3_26_24, GP_0_29_FN, FN_IP3_22_21, @@ -3186,9 +3186,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_3_FN, FN_A17, GP_0_2_FN, FN_IP0_7_6, GP_0_1_FN, FN_AVS2, - GP_0_0_FN, FN_AVS1 } + GP_0_0_FN, FN_AVS1 )) }, - { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1, GROUP( GP_1_31_FN, FN_IP5_23_21, GP_1_30_FN, FN_IP5_20_17, GP_1_29_FN, FN_IP5_16_15, @@ -3220,9 +3220,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_3_FN, FN_IP4_10_8, GP_1_2_FN, FN_IP4_7_5, GP_1_1_FN, FN_IP4_4_2, - GP_1_0_FN, FN_IP4_1_0 } + GP_1_0_FN, FN_IP4_1_0 )) }, - { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1, GROUP( GP_2_31_FN, FN_IP10_28_26, GP_2_30_FN, FN_IP10_25_24, GP_2_29_FN, FN_IP10_23_21, @@ -3254,9 +3254,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_3_FN, FN_IP8_24_23, GP_2_2_FN, FN_IP8_22_21, GP_2_1_FN, FN_IP8_20, - GP_2_0_FN, FN_IP5_27_24 } + GP_2_0_FN, FN_IP5_27_24 )) }, - { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1, GROUP( GP_3_31_FN, FN_IP6_3_2, GP_3_30_FN, FN_IP6_1_0, GP_3_29_FN, FN_IP5_30_29, @@ -3288,9 +3288,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_3_FN, FN_IP11_8_6, GP_3_2_FN, FN_IP11_5_3, GP_3_1_FN, FN_IP11_2_0, - GP_3_0_FN, FN_IP10_31_29 } + GP_3_0_FN, FN_IP10_31_29 )) }, - { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1, GROUP( GP_4_31_FN, FN_IP8_19, GP_4_30_FN, FN_IP8_18, GP_4_29_FN, FN_IP8_17_16, @@ -3322,9 +3322,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_3_FN, FN_IP6_11_9, GP_4_2_FN, FN_IP6_8, GP_4_1_FN, FN_IP6_7_6, - GP_4_0_FN, FN_IP6_5_4 } + GP_4_0_FN, FN_IP6_5_4 )) }, - { PINMUX_CFG_REG("GPSR5", 0xfffc0018, 32, 1) { + { PINMUX_CFG_REG("GPSR5", 0xfffc0018, 32, 1, GROUP( GP_5_31_FN, FN_IP3_5, GP_5_30_FN, FN_IP3_4, GP_5_29_FN, FN_IP3_3, @@ -3356,9 +3356,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_3_FN, FN_A4, GP_5_2_FN, FN_A3, GP_5_1_FN, FN_A2, - GP_5_0_FN, FN_A1 } + GP_5_0_FN, FN_A1 )) }, - { PINMUX_CFG_REG("GPSR6", 0xfffc001c, 32, 1) { + { PINMUX_CFG_REG("GPSR6", 0xfffc001c, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -3373,7 +3373,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_6_3_FN, FN_IP3_15, GP_6_2_FN, FN_IP3_8, GP_6_1_FN, FN_IP3_7, - GP_6_0_FN, FN_IP3_6 } + GP_6_0_FN, FN_IP3_6 )) }, { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32, diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index 202638b9cb54..8b5ced30b3ee 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -4745,7 +4745,7 @@ static const struct sh_pfc_function pinmux_functions[] = { }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { - { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP( GP_0_31_FN, FN_IP3_17_15, GP_0_30_FN, FN_IP3_14_12, GP_0_29_FN, FN_IP3_11_8, @@ -4777,9 +4777,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_3_FN, FN_IP0_11_9, GP_0_2_FN, FN_IP0_8_6, GP_0_1_FN, FN_IP0_5_3, - GP_0_0_FN, FN_IP0_2_0 } + GP_0_0_FN, FN_IP0_2_0 )) }, - { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP( 0, 0, 0, 0, GP_1_29_FN, FN_IP6_13_11, @@ -4811,9 +4811,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_3_FN, FN_IP3_28_26, GP_1_2_FN, FN_IP3_25_23, GP_1_1_FN, FN_IP3_22_20, - GP_1_0_FN, FN_IP3_19_18, } + GP_1_0_FN, FN_IP3_19_18, )) }, - { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP( 0, 0, 0, 0, GP_2_29_FN, FN_IP7_15_13, @@ -4845,9 +4845,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_3_FN, FN_IP8_3_2, GP_2_2_FN, FN_IP8_1_0, GP_2_1_FN, FN_IP7_30_29, - GP_2_0_FN, FN_IP7_28_27 } + GP_2_0_FN, FN_IP7_28_27 )) }, - { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP( GP_3_31_FN, FN_IP11_21_18, GP_3_30_FN, FN_IP11_17_15, GP_3_29_FN, FN_IP11_14_13, @@ -4879,9 +4879,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_3_FN, FN_IP9_3_2, GP_3_2_FN, FN_IP9_1_0, GP_3_1_FN, FN_IP8_30_29, - GP_3_0_FN, FN_IP8_28 } + GP_3_0_FN, FN_IP8_28 )) }, - { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP( GP_4_31_FN, FN_IP14_18_16, GP_4_30_FN, FN_IP14_15_12, GP_4_29_FN, FN_IP14_11_9, @@ -4913,9 +4913,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_3_FN, FN_IP11_31_30, GP_4_2_FN, FN_IP11_29_27, GP_4_1_FN, FN_IP11_26_24, - GP_4_0_FN, FN_IP11_23_22 } + GP_4_0_FN, FN_IP11_23_22 )) }, - { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { + { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP( GP_5_31_FN, FN_IP7_24_22, GP_5_30_FN, FN_IP7_21_19, GP_5_29_FN, FN_IP7_18_16, @@ -4947,7 +4947,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_3_FN, FN_IP14_30_28, GP_5_2_FN, FN_IP14_27_25, GP_5_1_FN, FN_IP14_24_22, - GP_5_0_FN, FN_IP14_21_19 } + GP_5_0_FN, FN_IP14_21_19 )) }, { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, 1, 4, 4, 3, 4, 4, 3, 3, 3, 3) { diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index d21a520695db..b96c9a207cf8 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -5428,7 +5428,7 @@ static const struct { }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { - { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP( GP_0_31_FN, FN_IP1_22_20, GP_0_30_FN, FN_IP1_19_17, GP_0_29_FN, FN_IP1_16_14, @@ -5460,9 +5460,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_3_FN, FN_IP0_3, GP_0_2_FN, FN_IP0_2, GP_0_1_FN, FN_IP0_1, - GP_0_0_FN, FN_IP0_0, } + GP_0_0_FN, FN_IP0_0, )) }, - { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5494,9 +5494,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_3_FN, FN_IP2_2_0, GP_1_2_FN, FN_IP1_31_29, GP_1_1_FN, FN_IP1_28_26, - GP_1_0_FN, FN_IP1_25_23, } + GP_1_0_FN, FN_IP1_25_23, )) }, - { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP( GP_2_31_FN, FN_IP6_7_6, GP_2_30_FN, FN_IP6_5_3, GP_2_29_FN, FN_IP6_2_0, @@ -5528,9 +5528,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_3_FN, FN_IP4_4_2, GP_2_2_FN, FN_IP4_1_0, GP_2_1_FN, FN_IP3_30_28, - GP_2_0_FN, FN_IP3_27_25 } + GP_2_0_FN, FN_IP3_27_25 )) }, - { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP( GP_3_31_FN, FN_IP9_18_17, GP_3_30_FN, FN_IP9_16, GP_3_29_FN, FN_IP9_15_13, @@ -5562,9 +5562,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_3_FN, FN_IP7_12_11, GP_3_2_FN, FN_IP7_10_9, GP_3_1_FN, FN_IP7_8_6, - GP_3_0_FN, FN_IP7_5_3 } + GP_3_0_FN, FN_IP7_5_3 )) }, - { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP( GP_4_31_FN, FN_IP15_5_4, GP_4_30_FN, FN_IP15_3_2, GP_4_29_FN, FN_IP15_1_0, @@ -5596,9 +5596,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_3_FN, FN_IP9_24_23, GP_4_2_FN, FN_IP9_22_21, GP_4_1_FN, FN_IP9_20_19, - GP_4_0_FN, FN_VI0_CLK } + GP_4_0_FN, FN_VI0_CLK )) }, - { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { + { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP( GP_5_31_FN, FN_IP3_24_22, GP_5_30_FN, FN_IP13_9_7, GP_5_29_FN, FN_IP13_6_5, @@ -5630,9 +5630,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_3_FN, FN_IP11_18_17, GP_5_2_FN, FN_IP11_16_15, GP_5_1_FN, FN_IP11_14_12, - GP_5_0_FN, FN_IP11_11_9 } + GP_5_0_FN, FN_IP11_11_9 )) }, - { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) { + { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP( GP_6_31_FN, FN_DU0_DOTCLKIN, GP_6_30_FN, FN_USB1_OVC, GP_6_29_FN, FN_IP14_31_29, @@ -5664,9 +5664,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_6_3_FN, FN_IP13_13, GP_6_2_FN, FN_IP13_12, GP_6_1_FN, FN_IP13_11, - GP_6_0_FN, FN_IP13_10 } + GP_6_0_FN, FN_IP13_10 )) }, - { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) { + { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -5698,7 +5698,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_7_3_FN, FN_IP15_26_24, GP_7_2_FN, FN_IP15_23_21, GP_7_1_FN, FN_IP15_20_18, - GP_7_0_FN, FN_IP15_17_15 } + GP_7_0_FN, FN_IP15_17_15 )) }, { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, 1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, 1, 1, 1, 1, diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c index d36da5652de6..624dcc1c81bd 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c @@ -1988,7 +1988,7 @@ static const struct sh_pfc_function pinmux_functions[] = { }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { - { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { + { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2020,9 +2020,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_3_FN, FN_IP0_3, GP_0_2_FN, FN_IP0_2, GP_0_1_FN, FN_IP0_1, - GP_0_0_FN, FN_IP0_0 } + GP_0_0_FN, FN_IP0_0 )) }, - { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { + { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2054,9 +2054,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_3_FN, FN_IP1_8, GP_1_2_FN, FN_IP1_7, GP_1_1_FN, FN_IP1_6, - GP_1_0_FN, FN_IP1_5, } + GP_1_0_FN, FN_IP1_5, )) }, - { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { + { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP( GP_2_31_FN, FN_A15, GP_2_30_FN, FN_A14, GP_2_29_FN, FN_A13, @@ -2088,9 +2088,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_3_FN, FN_D3, GP_2_2_FN, FN_D2, GP_2_1_FN, FN_D1, - GP_2_0_FN, FN_D0 } + GP_2_0_FN, FN_D0 )) }, - { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { + { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2122,9 +2122,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_3_FN, FN_A19, GP_3_2_FN, FN_A18, GP_3_1_FN, FN_A17, - GP_3_0_FN, FN_A16 } + GP_3_0_FN, FN_A16 )) }, - { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { + { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2156,9 +2156,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_3_FN, FN_VI0_VSYNC_N, GP_4_2_FN, FN_VI0_HSYNC_N, GP_4_1_FN, FN_VI0_CLKENB, - GP_4_0_FN, FN_VI0_CLK } + GP_4_0_FN, FN_VI0_CLK )) }, - { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { + { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2190,9 +2190,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_3_FN, FN_VI1_VSYNC_N, GP_5_2_FN, FN_VI1_HSYNC_N, GP_5_1_FN, FN_VI1_CLKENB, - GP_5_0_FN, FN_VI1_CLK } + GP_5_0_FN, FN_VI1_CLK )) }, - { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) { + { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2224,9 +2224,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_6_3_FN, FN_IP2_3, GP_6_2_FN, FN_IP2_2, GP_6_1_FN, FN_IP2_1, - GP_6_0_FN, FN_IP2_0 } + GP_6_0_FN, FN_IP2_0 )) }, - { PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1) { + { PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2258,9 +2258,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_7_3_FN, FN_IP3_3, GP_7_2_FN, FN_IP3_2, GP_7_1_FN, FN_IP3_1, - GP_7_0_FN, FN_IP3_0 } + GP_7_0_FN, FN_IP3_0 )) }, - { PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1) { + { PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2292,9 +2292,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_8_3_FN, FN_IP4_3_2, GP_8_2_FN, FN_IP4_1, GP_8_1_FN, FN_IP4_0, - GP_8_0_FN, FN_VI4_CLK } + GP_8_0_FN, FN_VI4_CLK )) }, - { PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1) { + { PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1, GROUP( 0, 0, 0, 0, 0, 0, @@ -2326,9 +2326,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_9_3_FN, FN_IP5_2, GP_9_2_FN, FN_IP5_1, GP_9_1_FN, FN_IP5_0, - GP_9_0_FN, FN_VI5_CLK } + GP_9_0_FN, FN_VI5_CLK )) }, - { PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1) { + { PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1, GROUP( GP_10_31_FN, FN_CAN1_RX, GP_10_30_FN, FN_CAN1_TX, GP_10_29_FN, FN_CAN_CLK, @@ -2360,9 +2360,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_10_3_FN, FN_IP6_2, GP_10_2_FN, FN_HRTS0_N, GP_10_1_FN, FN_IP6_1, - GP_10_0_FN, FN_IP6_0 } + GP_10_0_FN, FN_IP6_0 )) }, - { PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1) { + { PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1, GROUP( 0, 0, 0, 0, GP_11_29_FN, FN_AVS2, @@ -2394,7 +2394,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_11_3_FN, FN_IP7_6, GP_11_2_FN, FN_IP7_5_4, GP_11_1_FN, FN_IP7_3_2, - GP_11_0_FN, FN_IP7_1_0 } + GP_11_0_FN, FN_IP7_1_0 )) }, { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32, 4, 4, diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c index d24ba71649a1..6af1aeae64fd 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c @@ -4618,7 +4618,7 @@ static const struct sh_pfc_function pinmux_functions[] = { }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { - { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { |