diff options
author | Sudarsana Reddy Kalluru <skalluru@marvell.com> | 2020-07-04 10:13:43 +0530 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2020-07-04 17:51:07 -0700 |
commit | cdf711f20b23087a96811e92f9600a9cf5ea23d6 (patch) | |
tree | 2aba5798e70fb5a3e09b83ccee5db5d9885318c0 | |
parent | 4365f35b12447118a1193b9a20e512da65034110 (diff) |
bnx2x: Add support for idlechk tests.
This patch populates a database of idlechk tests (registers and
predicates) and performs the idlechk using this data.
Signed-off-by: Sudarsana Reddy Kalluru <skalluru@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r-- | drivers/net/ethernet/broadcom/bnx2x/Makefile | 2 | ||||
-rw-r--r-- | drivers/net/ethernet/broadcom/bnx2x/bnx2x.h | 10 | ||||
-rw-r--r-- | drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c | 7 | ||||
-rw-r--r-- | drivers/net/ethernet/broadcom/bnx2x/bnx2x_self_test.c | 3183 | ||||
-rw-r--r-- | drivers/net/ethernet/broadcom/bnx2x/bnx2x_stats.c | 2 |
5 files changed, 3196 insertions, 8 deletions
diff --git a/drivers/net/ethernet/broadcom/bnx2x/Makefile b/drivers/net/ethernet/broadcom/bnx2x/Makefile index 9fdfaa269af9..2523cfc7527d 100644 --- a/drivers/net/ethernet/broadcom/bnx2x/Makefile +++ b/drivers/net/ethernet/broadcom/bnx2x/Makefile @@ -5,5 +5,5 @@ obj-$(CONFIG_BNX2X) += bnx2x.o -bnx2x-y := bnx2x_main.o bnx2x_link.o bnx2x_cmn.o bnx2x_ethtool.o bnx2x_stats.o bnx2x_dcb.o bnx2x_sp.o +bnx2x-y := bnx2x_main.o bnx2x_link.o bnx2x_cmn.o bnx2x_ethtool.o bnx2x_stats.o bnx2x_dcb.o bnx2x_sp.o bnx2x_self_test.o bnx2x-$(CONFIG_BNX2X_SRIOV) += bnx2x_vfpf.o bnx2x_sriov.o diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h index 4f5b2b81be3d..dee61d96680e 100644 --- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h +++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h @@ -1979,6 +1979,9 @@ struct bnx2x_func_init_params { #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) +/*self test*/ +int bnx2x_idle_chk(struct bnx2x *bp); + /** * bnx2x_set_mac_one - configure a single MAC address * @@ -2430,13 +2433,6 @@ int bnx2x_compare_fw_ver(struct bnx2x *bp, u32 load_code, bool print_err); #define HC_SEG_ACCESS_ATTN 4 #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/ -static const u32 dmae_reg_go_c[] = { - DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, - DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, - DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, - DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 -}; - void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev); void bnx2x_notify_link_changed(struct bnx2x *bp); diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c index ea60cd436f5e..41aac4f7634a 100644 --- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c +++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c @@ -276,6 +276,13 @@ static const struct pci_device_id bnx2x_pci_tbl[] = { MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl); +const u32 dmae_reg_go_c[] = { + DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, + DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, + DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, + DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 +}; + /* Global resources for unloading a previously loaded device */ #define BNX2X_PREV_WAIT_NEEDED 1 static DEFINE_SEMAPHORE(bnx2x_prev_sem); diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_self_test.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_self_test.c new file mode 100644 index 000000000000..48f63ef2e6ea --- /dev/null +++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_self_test.c @@ -0,0 +1,3183 @@ +// SPDX-License-Identifier: GPL-2.0 +#include <linux/kernel.h> +#include <linux/netdevice.h> +#include "bnx2x.h" + +#define NA 0xCD + +#define IDLE_CHK_E1 0x01 +#define IDLE_CHK_E1H 0x02 +#define IDLE_CHK_E2 0x04 +#define IDLE_CHK_E3A0 0x08 +#define IDLE_CHK_E3B0 0x10 + +#define IDLE_CHK_ERROR 1 +#define IDLE_CHK_ERROR_NO_TRAFFIC 2 +#define IDLE_CHK_WARNING 3 + +#define MAX_FAIL_MSG 256 + +/* statistics and error reporting */ +static int idle_chk_errors, idle_chk_warnings; + +/* masks for all chip types */ +static int is_e1, is_e1h, is_e2, is_e3a0, is_e3b0; + +/* struct for the argument list for a predicate in the self test databasei */ +struct st_pred_args { + u32 val1; /* value read from first register */ + u32 val2; /* value read from second register, if applicable */ + u32 imm1; /* 1st value in predicate condition, left-to-right */ + u32 imm2; /* 2nd value in predicate condition, left-to-right */ + u32 imm3; /* 3rd value in predicate condition, left-to-right */ + u32 imm4; /* 4th value in predicate condition, left-to-right */ +}; + +/* struct representing self test record - a single test */ +struct st_record { + u8 chip_mask; + u8 macro; + u32 reg1; + u32 reg2; + u16 loop; + u16 incr; + int (*bnx2x_predicate)(struct st_pred_args *pred_args); + u32 reg3; + u8 severity; + char *fail_msg; + struct st_pred_args pred_args; +}; + +/* predicates for self test */ +static int peq(struct st_pred_args *args) +{ + return (args->val1 == args->imm1); +} + +static int pneq(struct st_pred_args *args) +{ + return (args->val1 != args->imm1); +} + +static int pand_neq(struct st_pred_args *args) +{ + return ((args->val1 & args->imm1) != args->imm2); +} + +static int pand_neq_x2(struct st_pred_args *args) +{ + return (((args->val1 & args->imm1) != args->imm2) && + ((args->val1 & args->imm3) != args->imm4)); +} + +static int pneq_err(struct st_pred_args *args) +{ + return ((args->val1 != args->imm1) && (idle_chk_errors > args->imm2)); +} + +static int pgt(struct st_pred_args *args) +{ + return (args->val1 > args->imm1); +} + +static int pneq_r2(struct st_pred_args *args) +{ + return (args->val1 != args->val2); +} + +static int plt_sub_r2(struct st_pred_args *args) +{ + return (args->val1 < (args->val2 - args->imm1)); +} + +static int pne_sub_r2(struct st_pred_args *args) +{ + return (args->val1 != (args->val2 - args->imm1)); +} + +static int prsh_and_neq(struct st_pred_args *args) +{ + return (((args->val1 >> args->imm1) & args->imm2) != args->imm3); +} + +static int peq_neq_r2(struct st_pred_args *args) +{ + return ((args->val1 == args->imm1) && (args->val2 != args->imm2)); +} + +static int peq_neq_neq_r2(struct st_pred_args *args) +{ + return ((args->val1 == args->imm1) && (args->val2 != args->imm2) && + (args->val2 != args->imm3)); +} + +/* struct holding the database of self test checks (registers and predicates) */ +/* lines start from 2 since line 1 is heading in csv */ +#define ST_DB_LINES 468 +static struct st_record st_database[ST_DB_LINES] = { +/*line 2*/{(0x3), 1, 0x2114, + NA, 1, 0, pand_neq, + NA, IDLE_CHK_ERROR, + "PCIE: ucorr_err_status is not 0", + {NA, NA, 0x0FF010, 0, NA, NA} }, + +/*line 3*/{(0x3), 1, 0x2114, + NA, 1, 0, pand_neq, + NA, IDLE_CHK_WARNING, + "PCIE: ucorr_err_status - Unsupported request error", + {NA, NA, 0x100000, 0, NA, NA} }, + +/*line 4*/{(0x3), 1, 0x2120, + NA, 1, 0, pand_neq_x2, + NA, IDLE_CHK_WARNING, + "PCIE: corr_err_status is not 0x2000", + {NA, NA, 0x31C1, 0x2000, 0x31C1, 0} }, + +/*line 5*/{(0x3), 1, 0x2814, + NA, 1, 0, pand_neq, + NA, IDLE_CHK_ERROR, + "PCIE: attentions register is not 0x40100", + {NA, NA, ~0x40100, 0, NA, NA} }, + +/*line 6*/{(0x2), 1, 0x281c, + NA, 1, 0, pand_neq, + NA, IDLE_CHK_ERROR, + "PCIE: attentions register is not 0x40040100", + {NA, NA, ~0x40040100, 0, NA, NA} }, + +/*line 7*/{(0x2), 1, 0x2820, + NA, 1, 0, pand_neq, + NA, IDLE_CHK_ERROR, + "PCIE: attentions register is not 0x40040100", + {NA, NA, ~0x40040100, 0, NA, NA} }, + +/*line 8*/{(0x3), 1, PXP2_REG_PGL_EXP_ROM2, + NA, 1, 0, pneq, + NA, IDLE_CHK_WARNING, + "PXP2: There are outstanding read requests. Not all completios have arrived for read requests on tags that are marked with 0", + {NA, NA, 0xffffffff, NA, NA, NA} }, + +/*line 9*/{(0x3), 2, 0x212c, + NA, 4, 4, pneq_err, + NA, IDLE_CHK_WARNING, + "PCIE: error packet header is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 10*/{(0x1C), 1, 0x2104, + NA, 1, 0, pand_neq, + NA, IDLE_CHK_ERROR, + "PCIE: ucorr_err_status is not 0", + {NA, NA, 0x0FD010, 0, NA, NA} }, + +/*line 11*/{(0x1C), 1, 0x2104, + NA, 1, 0, pand_neq, + NA, IDLE_CHK_WARNING, + "PCIE: ucorr_err_status - Unsupported request error", + {NA, NA, 0x100000, 0, NA, NA} }, + +/*line 12*/{(0x1C), 1, 0x2104, + NA, 1, 0, pand_neq, + NA, IDLE_CHK_WARNING, + "PCIE: ucorr_err_status - Flow Control Protocol Error", + {NA, NA, 0x2000, 0, NA, NA} }, + +/*line 13*/{(0x1C), 1, 0x2110, + NA, 1, 0, pand_neq_x2, + NA, IDLE_CHK_WARNING, + "PCIE: corr_err_status is not 0x2000", + {NA, NA, 0x31C1, 0x2000, 0x31C1, 0} }, + +/*line 14*/{(0x1C), 1, 0x2814, + NA, 1, 0, pand_neq, + NA, IDLE_CHK_WARNING, + "PCIE: TTX_BRIDGE_FORWARD_ERR - Received master request while BME was 0", + {NA, NA, 0x2000000, 0, NA, NA} }, + +/*line 15*/{(0x1C), 1, 0x2814, + NA, 1, 0, pand_neq, + NA, IDLE_CHK_ERROR, + "PCIE: Func 0 1: attentions register is not 0x2040902", + {NA, NA, ~0x2040902, 0, NA, NA} }, + +/*line 16*/{(0x1C), 1, 0x2854, + NA, 1, 0, pand_neq, + NA, IDLE_CHK_ERROR, + "PCIE: Func 2 3 4: attentions register is not 0x10240902", + {NA, NA, ~0x10240902, 0, NA, NA} }, + +/*line 17*/{(0x1C), 1, 0x285c, + NA, 1, 0, pand_neq, + NA, IDLE_CHK_ERROR, + "PCIE: Func 5 6 7: attentions register is not 0x10240902", + {NA, NA, ~0x10240902, 0, NA, NA} }, + +/*line 18*/{(0x18), 1, 0x3040, + NA, 1, 0, pand_neq, + NA, IDLE_CHK_ERROR, + "PCIE: Overflow in DLP2TLP buffer", + {NA, NA, 0x2, 0, NA, NA} }, + +/*line 19*/{(0x1C), 1, PXP2_REG_PGL_EXP_ROM2, + NA, 1, 0, pneq, + NA, IDLE_CHK_WARNING, + "PXP2: There are outstanding read requests for tags 0-31. Not all completios have arrived for read requests on tags that are marked with 0", + {NA, NA, 0xffffffff, NA, NA, NA} }, + +/*line 20*/{(0x1C), 2, 0x211c, + NA, 4, 4, pneq_err, + NA, IDLE_CHK_WARNING, + "PCIE: error packet header is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 21*/{(0x1C), 1, PGLUE_B_REG_INCORRECT_RCV_DETAILS, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR, + "PGLUE_B: Packet received from PCIe not according to the rules", + {NA, NA, 0, NA, NA, NA} }, + +/*line 22*/{(0x1C), 1, PGLUE_B_REG_WAS_ERROR_VF_31_0, + NA, 1, 0, pneq, + NA, IDLE_CHK_WARNING, + "PGLUE_B: was_error for VFs 0-31 is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 23*/{(0x1C), 1, PGLUE_B_REG_WAS_ERROR_VF_63_32, + NA, 1, 0, pneq, + NA, IDLE_CHK_WARNING, + "PGLUE_B: was_error for VFs 32-63 is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 24*/{(0x1C), 1, PGLUE_B_REG_WAS_ERROR_VF_95_64, + NA, 1, 0, pneq, + NA, IDLE_CHK_WARNING, + "PGLUE_B: was_error for VFs 64-95 is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 25*/{(0x1C), 1, PGLUE_B_REG_WAS_ERROR_VF_127_96, + NA, 1, 0, pneq, + NA, IDLE_CHK_WARNING, + "PGLUE_B: was_error for VFs 96-127 is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 26*/{(0x1C), 1, PGLUE_B_REG_WAS_ERROR_PF_7_0, + NA, 1, 0, pneq, + NA, IDLE_CHK_WARNING, + "PGLUE_B: was_error for PFs 0-7 is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 27*/{(0x1C), 1, PGLUE_B_REG_RX_ERR_DETAILS, + NA, 1, 0, pneq, + NA, IDLE_CHK_WARNING, + "PGLUE_B: Completion received with error. (2:0) - PFID. (3) - VF_VALID. (9:4) - VFID. (11:10) - Error code : 0 - Completion Timeout; 1 - Unsupported Request; 2 - Completer Abort. (12) - valid bit", + {NA, NA, 0, NA, NA, NA} }, + +/*line 28*/{(0x1C), 1, PGLUE_B_REG_RX_TCPL_ERR_DETAILS, + NA, 1, 0, pneq, + NA, IDLE_CHK_WARNING, + "PGLUE_B: ATS TCPL received with error. (2:0) - PFID. (3) - VF_VALID. (9:4) - VFID. (11:10) - Error code : 0 - Completion Timeout ; 1 - Unsupported Request; 2 - Completer Abort. (16:12) - OTB Entry ID. (17) - valid bit", + {NA, NA, 0, NA, NA, NA} }, + +/*line 29*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_WR_ADD_31_0, + NA, 1, 0, pneq, + NA, IDLE_CHK_WARNING, + "PGLUE_B: Error in master write. Address(31:0) is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 30*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_WR_ADD_63_32, + NA, 1, 0, pneq, + NA, IDLE_CHK_WARNING, + "PGLUE_B: Error in master write. Address(63:32) is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 31*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_WR_DETAILS, + NA, 1, 0, pneq, + NA, IDLE_CHK_WARNING, + "PGLUE_B: Error in master write. Error details register is not 0. (4:0) VQID. (23:21) - PFID. (24) - VF_VALID. (30:25) - VFID", + {NA, NA, 0, NA, NA, NA} }, + +/*line 32*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_WR_DETAILS2, + NA, 1, 0, pneq, + NA, IDLE_CHK_WARNING, + "PGLUE_B: Error in master write. Error details 2nd register is not 0. (21) - was_error set; (22) - BME cleared; (23) - FID_enable cleared; (24) - VF with parent PF FLR_request or IOV_disable_request", + {NA, NA, 0, NA, NA, NA} }, + +/*line 33*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_RD_ADD_31_0, + NA, 1, 0, pneq, + NA, IDLE_CHK_WARNING, + "PGLUE: Error in master read address(31:0) is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 34*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_RD_ADD_63_32, + NA, 1, 0, pneq, + NA, IDLE_CHK_WARNING, + "PGLUE_B: Error in master read address(63:32) is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 35*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_RD_DETAILS, + NA, 1, 0, pneq, + NA, IDLE_CHK_WARNING, + "PGLUE_B: Error in master read Error details register is not 0. (4:0) VQID. (23:21) - PFID. (24) - VF_VALID. (30:25) - VFID", + {NA, NA, 0, NA, NA, NA} }, + +/*line 36*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_RD_DETAILS2, + NA, 1, 0, pneq, + NA, IDLE_CHK_WARNING, + "PGLUE_B: Error in master read Error details 2nd register is not 0. (21) - was_error set; (22) - BME cleared; (23) - FID_enable cleared; (24) - VF with parent PF FLR_request or IOV_disable_request", + {NA, NA, 0, NA, NA, NA} }, + +/*line 37*/{(0x1C), 1, PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS, + NA, 1, 0, pneq, + NA, IDLE_CHK_WARNING, + "PGLUE_B: Target VF length violation access", + {NA, NA, 0, NA, NA, NA} }, + +/*line 38*/{(0x1C), 1, PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS, + NA, 1, 0, pneq, + NA, IDLE_CHK_WARNING, + "PGLUE_B: Target VF GRC space access failed permission check", + {NA, NA, 0, NA, NA, NA} }, + +/*line 39*/{(0x1C), 1, PGLUE_B_REG_TAGS_63_32, + NA, 1, 0, pneq, + NA, IDLE_CHK_WARNING, + "PGLUE_B: There are outstanding read requests for tags 32-63. Not all completios have arrived for read requests on tags that are marked with 0", + {NA, NA, 0xffffffff, NA, NA, NA} }, + +/*line 40*/{(0x1C), 3, PXP_REG_HST_VF_DISABLED_ERROR_VALID, + PXP_REG_HST_VF_DISABLED_ERROR_DATA, 1, 0, pneq, + NA, IDLE_CHK_WARNING, + "PXP: Access to disabled VF took place", + {NA, NA, 0, NA, NA, NA} }, + +/*line 41*/{(0x1C), 1, PXP_REG_HST_PER_VIOLATION_VALID, + NA, 1, 0, pneq, + NA, IDLE_CHK_WARNING, + "PXP: Zone A permission violation occurred", + {NA, NA, 0, NA, NA, NA} }, + +/*line 42*/{(0x1C), 1, PXP_REG_HST_INCORRECT_ACCESS_VALID, + NA, 1, 0, pneq, + NA, IDLE_CHK_WARNING, + "PXP: Incorrect transaction took place", + {NA, NA, 0, NA, NA, NA} }, + +/*line 43*/{(0x1C), 1, PXP2_REG_RD_CPL_ERR_DETAILS, + NA, 1, 0, pneq, + NA, IDLE_CHK_WARNING, + "PXP2: Completion received with error. Error details register is not 0. (15:0) - ECHO. (28:16) - Sub Request length plus start_offset_2_0 minus 1", + {NA, NA, 0, NA, NA, NA} }, + +/*line 44*/{(0x1C), 1, PXP2_REG_RD_CPL_ERR_DETAILS2, + NA, 1, 0, pneq, + NA, IDLE_CHK_WARNING, + "PXP2: Completion received with error. Error details 2nd register is not 0. (4:0) - VQ ID. (8:5) - client ID. (9) - valid bit", + {NA, NA, 0, NA, NA, NA} }, + +/*line 45*/{(0x1F), 1, PXP2_REG_RQ_VQ0_ENTRY_CNT, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: VQ0 is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 46*/{(0x1F), 1, PXP2_REG_RQ_VQ1_ENTRY_CNT, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: VQ1 is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 47*/{(0x1F), 1, PXP2_REG_RQ_VQ2_ENTRY_CNT, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: VQ2 is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 48*/{(0x1F), 1, PXP2_REG_RQ_VQ3_ENTRY_CNT, + NA, 1, 0, pgt, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: VQ3 is not empty", + {NA, NA, 2, NA, NA, NA} }, + +/*line 49*/{(0x1F), 1, PXP2_REG_RQ_VQ4_ENTRY_CNT, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: VQ4 is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 50*/{(0x1F), 1, PXP2_REG_RQ_VQ5_ENTRY_CNT, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: VQ5 is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 51*/{(0x1F), 1, PXP2_REG_RQ_VQ6_ENTRY_CNT, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: VQ6 is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 52*/{(0x1F), 1, PXP2_REG_RQ_VQ7_ENTRY_CNT, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: VQ7 is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 53*/{(0x1F), 1, PXP2_REG_RQ_VQ8_ENTRY_CNT, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: VQ8 is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 54*/{(0x1F), 1, PXP2_REG_RQ_VQ9_ENTRY_CNT, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: VQ9 is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 55*/{(0x1F), 1, PXP2_REG_RQ_VQ10_ENTRY_CNT, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: VQ10 is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 56*/{(0x1F), 1, PXP2_REG_RQ_VQ11_ENTRY_CNT, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: VQ11 is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 57*/{(0x1F), 1, PXP2_REG_RQ_VQ12_ENTRY_CNT, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: VQ12 is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 58*/{(0x1F), 1, PXP2_REG_RQ_VQ13_ENTRY_CNT, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: VQ13 is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 59*/{(0x1F), 1, PXP2_REG_RQ_VQ14_ENTRY_CNT, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: VQ14 is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 60*/{(0x1F), 1, PXP2_REG_RQ_VQ15_ENTRY_CNT, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: VQ15 is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 61*/{(0x1F), 1, PXP2_REG_RQ_VQ16_ENTRY_CNT, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: VQ16 is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 62*/{(0x1F), 1, PXP2_REG_RQ_VQ17_ENTRY_CNT, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: VQ17 is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 63*/{(0x1F), 1, PXP2_REG_RQ_VQ18_ENTRY_CNT, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: VQ18 is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 64*/{(0x1F), 1, PXP2_REG_RQ_VQ19_ENTRY_CNT, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: VQ19 is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 65*/{(0x1F), 1, PXP2_REG_RQ_VQ20_ENTRY_CNT, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: VQ20 is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 66*/{(0x1F), 1, PXP2_REG_RQ_VQ21_ENTRY_CNT, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: VQ21 is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 67*/{(0x1F), 1, PXP2_REG_RQ_VQ22_ENTRY_CNT, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: VQ22 is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 68*/{(0x1F), 1, PXP2_REG_RQ_VQ23_ENTRY_CNT, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: VQ23 is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 69*/{(0x1F), 1, PXP2_REG_RQ_VQ24_ENTRY_CNT, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: VQ24 is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 70*/{(0x1F), 1, PXP2_REG_RQ_VQ25_ENTRY_CNT, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: VQ25 is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 71*/{(0x1F), 1, PXP2_REG_RQ_VQ26_ENTRY_CNT, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: VQ26 is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 72*/{(0x1F), 1, PXP2_REG_RQ_VQ27_ENTRY_CNT, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: VQ27 is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 73*/{(0x1F), 1, PXP2_REG_RQ_VQ28_ENTRY_CNT, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: VQ28 is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 74*/{(0x1F), 1, PXP2_REG_RQ_VQ29_ENTRY_CNT, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: VQ29 is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 75*/{(0x1F), 1, PXP2_REG_RQ_VQ30_ENTRY_CNT, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: VQ30 is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 76*/{(0x1F), 1, PXP2_REG_RQ_VQ31_ENTRY_CNT, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: VQ31 is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 77*/{(0x1F), 1, PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: rq_ufifo_num_of_entry is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 78*/{(0x1F), 1, PXP2_REG_RQ_RBC_DONE, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR, + "PXP2: rq_rbc_done is not 1", + {NA, NA, 1, NA, NA, NA} }, + +/*line 79*/{(0x1F), 1, PXP2_REG_RQ_CFG_DONE, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR, + "PXP2: rq_cfg_done is not 1", + {NA, NA, 1, NA, NA, NA} }, + +/*line 80*/{(0x3), 1, PXP2_REG_PSWRQ_BW_CREDIT, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: rq_read_credit and rq_write_credit are not 3", + {NA, NA, 0x1B, NA, NA, NA} }, + +/*line 81*/{(0x1F), 1, PXP2_REG_RD_START_INIT, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR, + "PXP2: rd_start_init is not 1", + {NA, NA, 1, NA, NA, NA} }, + +/*line 82*/{(0x1F), 1, PXP2_REG_RD_INIT_DONE, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR, + "PXP2: rd_init_done is not 1", + {NA, NA, 1, NA, NA, NA} }, + +/*line 83*/{(0x1F), 3, PXP2_REG_RD_SR_CNT, + PXP2_REG_RD_SR_NUM_CFG, 1, 0, pne_sub_r2, + NA, IDLE_CHK_WARNING, + "PXP2: rd_sr_cnt is not equal to rd_sr_num_cfg", + {NA, NA, 1, NA, NA, NA} }, + +/*line 84*/{(0x1F), 3, PXP2_REG_RD_BLK_CNT, + PXP2_REG_RD_BLK_NUM_CFG, 1, 0, pneq_r2, + NA, IDLE_CHK_WARNING, + "PXP2: rd_blk_cnt is not equal to rd_blk_num_cfg", + {NA, NA, NA, NA, NA, NA} }, + +/*line 85*/{(0x1F), 3, PXP2_REG_RD_SR_CNT, + PXP2_REG_RD_SR_NUM_CFG, 1, 0, plt_sub_r2, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: There are more than two unused SRs", + {NA, NA, 3, NA, NA, NA} }, + +/*line 86*/{(0x1F), 3, PXP2_REG_RD_BLK_CNT, + PXP2_REG_RD_BLK_NUM_CFG, 1, 0, plt_sub_r2, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: There are more than two unused blocks", + {NA, NA, 2, NA, NA, NA} }, + +/*line 87*/{(0x1F), 1, PXP2_REG_RD_PORT_IS_IDLE_0, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: P0 All delivery ports are not idle", + {NA, NA, 1, NA, NA, NA} }, + +/*line 88*/{(0x1F), 1, PXP2_REG_RD_PORT_IS_IDLE_1, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: P1 All delivery ports are not idle", + {NA, NA, 1, NA, NA, NA} }, + +/*line 89*/{(0x1F), 2, PXP2_REG_RD_ALMOST_FULL_0, + NA, 11, 4, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: rd_almost_full is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 90*/{(0x1F), 1, PXP2_REG_RD_DISABLE_INPUTS, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR, + "PXP2: PSWRD inputs are disabled", + {NA, NA, 0, NA, NA, NA} }, + +/*line 91*/{(0x1F), 1, PXP2_REG_HST_HEADER_FIFO_STATUS, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: HST header FIFO status is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 92*/{(0x1F), 1, PXP2_REG_HST_DATA_FIFO_STATUS, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: HST data FIFO status is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 93*/{(0x3), 1, PXP2_REG_PGL_WRITE_BLOCKED, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR, + "PXP2: pgl_write_blocked is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 94*/{(0x3), 1, PXP2_REG_PGL_READ_BLOCKED, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR, + "PXP2: pgl_read_blocked is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 95*/{(0x1C), 1, PXP2_REG_PGL_WRITE_BLOCKED, + NA, 1, 0, pneq, + NA, IDLE_CHK_WARNING, + "PXP2: pgl_write_blocked is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 96*/{(0x1C), 1, PXP2_REG_PGL_READ_BLOCKED, + NA, 1, 0, pneq, + NA, IDLE_CHK_WARNING, + "PXP2: pgl_read_blocked is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 97*/{(0x1F), 1, PXP2_REG_PGL_TXW_CDTS, + NA, 1, 0, prsh_and_neq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "PXP2: There is data which is ready", + {NA, NA, 17, 1, 0, NA} }, + +/*line 98*/{(0x1F), 1, PXP_REG_HST_ARB_IS_IDLE, + NA, 1, 0, pneq, + NA, IDLE_CHK_WARNING, + "PXP: HST arbiter is not idle", + {NA, NA, 1, NA, NA, NA} }, + +/*line 99*/{(0x1F), 1, PXP_REG_HST_CLIENTS_WAITING_TO_ARB, + NA, 1, 0, pneq, + NA, IDLE_CHK_WARNING, + "PXP: HST one of the clients is waiting for delivery", + {NA, NA, 0, NA, NA, NA} }, + +/*line 100*/{(0x1E), 1, PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS, + NA, 1, 0, pneq, + NA, IDLE_CHK_WARNING, + "PXP: HST Close the gates: Discarding internal writes", + {NA, NA, 0, NA, NA, NA} }, + +/*line 101*/{(0x1E), 1, PXP_REG_HST_DISCARD_DOORBELLS_STATUS, + NA, 1, 0, pneq, + NA, IDLE_CHK_WARNING, + "PXP: HST Close the gates: Discarding doorbells", + {NA, NA, 0, NA, NA, NA} }, + +/*line 102*/{(0x1C), 1, PXP2_REG_RQ_GARB, + NA, 1, 0, pand_neq, + NA, IDLE_CHK_WARNING, + "PXP2: PSWRQ Close the gates is asserted. Check AEU AFTER_INVERT registers for parity errors", + {NA, NA, 0x1000, 0, NA, NA} }, + +/*line 103*/{(0x1F), 1, DMAE_REG_GO_C0, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "DMAE: command 0 go is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 104*/{(0x1F), 1, DMAE_REG_GO_C1, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "DMAE: command 1 go is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 105*/{(0x1F), 1, DMAE_REG_GO_C2, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "DMAE: command 2 go is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 106*/{(0x1F), 1, DMAE_REG_GO_C3, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "DMAE: command 3 go is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 107*/{(0x1F), 1, DMAE_REG_GO_C4, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "DMAE: command 4 go is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 108*/{(0x1F), 1, DMAE_REG_GO_C5, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "DMAE: command 5 go is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 109*/{(0x1F), 1, DMAE_REG_GO_C6, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "DMAE: command 6 go is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 110*/{(0x1F), 1, DMAE_REG_GO_C7, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "DMAE: command 7 go is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 111*/{(0x1F), 1, DMAE_REG_GO_C8, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "DMAE: command 8 go is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 112*/{(0x1F), 1, DMAE_REG_GO_C9, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "DMAE: command 9 go is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 113*/{(0x1F), 1, DMAE_REG_GO_C10, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "DMAE: command 10 go is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 114*/{(0x1F), 1, DMAE_REG_GO_C11, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "DMAE: command 11 go is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 115*/{(0x1F), 1, DMAE_REG_GO_C12, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "DMAE: command 12 go is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 116*/{(0x1F), 1, DMAE_REG_GO_C13, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "DMAE: command 13 go is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 117*/{(0x1F), 1, DMAE_REG_GO_C14, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "DMAE: command 14 go is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 118*/{(0x1F), 1, DMAE_REG_GO_C15, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "DMAE: command 15 go is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 119*/{(0x1F), 1, CFC_REG_ERROR_VECTOR, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR, + "CFC: error vector is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 120*/{(0x1F), 1, CFC_REG_NUM_LCIDS_ARRIVING, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR, + "CFC: number of arriving LCIDs is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 121*/{(0x1F), 1, CFC_REG_NUM_LCIDS_ALLOC, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR, + "CFC: number of alloc LCIDs is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 122*/{(0x1F), 1, CFC_REG_NUM_LCIDS_LEAVING, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR, + "CFC: number of leaving LCIDs is not 0", + {NA, NA, 0, NA, NA, NA} }, + +/*line 123*/{(0x1F), 7, CFC_REG_INFO_RAM, + CFC_REG_CID_CAM, (CFC_REG_INFO_RAM_SIZE >> 4), 16, peq_neq_neq_r2, + CFC_REG_ACTIVITY_COUNTER, IDLE_CHK_ERROR_NO_TRAFFIC, + "CFC: AC is neither 0 nor 2 on connType 0 (ETH)", + {NA, NA, 0, 0, 2, NA} }, + +/*line 124*/{(0x1F), 7, CFC_REG_INFO_RAM, + CFC_REG_CID_CAM, (CFC_REG_INFO_RAM_SIZE >> 4), 16, peq_neq_r2, + CFC_REG_ACTIVITY_COUNTER, IDLE_CHK_ERROR_NO_TRAFFIC, + "CFC: AC is not 0 on connType 1 (TOE)", + {NA, NA, 1, 0, NA, NA} }, + +/*line 125*/{(0x1F), 7, CFC_REG_INFO_RAM, + CFC_REG_CID_CAM, (CFC_REG_INFO_RAM_SIZE >> 4), 16, peq_neq_r2, + CFC_REG_ACTIVITY_COUNTER, IDLE_CHK_ERROR_NO_TRAFFIC, + "CFC: AC is not 0 on connType 3 (iSCSI)", + {NA, NA, 3, 0, NA, NA} }, + +/*line 126*/{(0x1F), 7, CFC_REG_INFO_RAM, + CFC_REG_CID_CAM, (CFC_REG_INFO_RAM_SIZE >> 4), 16, peq_neq_r2, + CFC_REG_ACTIVITY_COUNTER, IDLE_CHK_ERROR_NO_TRAFFIC, + "CFC: AC is not 0 on connType 4 (FCoE)", + {NA, NA, 4, 0, NA, NA} }, + +/*line 127*/{(0x1F), 2, QM_REG_QTASKCTR_0, + NA, 64, 4, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "QM: Queue is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 128*/{(0xF), 3, QM_REG_VOQCREDIT_0, + QM_REG_VOQINITCREDIT_0, 1, 0, pneq_r2, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "QM: VOQ_0, VOQ credit is not equal to initial credit", + {NA, NA, NA, NA, NA, NA} }, + +/*line 129*/{(0xF), 3, QM_REG_VOQCREDIT_1, + QM_REG_VOQINITCREDIT_1, 1, 0, pneq_r2, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "QM: VOQ_1, VOQ credit is not equal to initial credit", + {NA, NA, NA, NA, NA, NA} }, + +/*line 130*/{(0xF), 3, QM_REG_VOQCREDIT_4, + QM_REG_VOQINITCREDIT_4, 1, 0, pneq_r2, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "QM: VOQ_4, VOQ credit is not equal to initial credit", + {NA, NA, NA, NA, NA, NA} }, + +/*line 131*/{(0x3), 3, QM_REG_PORT0BYTECRD, + QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "QM: P0 Byte credit is not equal to initial credit", + {NA, NA, NA, NA, NA, NA} }, + +/*line 132*/{(0x3), 3, QM_REG_PORT1BYTECRD, + QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "QM: P1 Byte credit is not equal to initial credit", + {NA, NA, NA, NA, NA, NA} }, + +/*line 133*/{(0x1F), 1, CCM_REG_CAM_OCCUP, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "CCM: XX protection CAM is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 134*/{(0x1F), 1, TCM_REG_CAM_OCCUP, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "TCM: XX protection CAM is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 135*/{(0x1F), 1, UCM_REG_CAM_OCCUP, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "UCM: XX protection CAM is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 136*/{(0x1F), 1, XCM_REG_CAM_OCCUP, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "XCM: XX protection CAM is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 137*/{(0x1F), 1, BRB1_REG_NUM_OF_FULL_BLOCKS, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "BRB1: BRB is not empty", + {NA, NA, 0, NA, NA, NA} }, + +/*line 138*/{(0x1F), 1, CSEM_REG_SLEEP_THREADS_VALID, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "CSEM: There are sleeping threads", + {NA, NA, 0, NA, NA, NA} }, + +/*line 139*/{(0x1F), 1, TSEM_REG_SLEEP_THREADS_VALID, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "TSEM: There are sleeping threads", + {NA, NA, 0, NA, NA, NA} }, + +/*line 140*/{(0x1F), 1, USEM_REG_SLEEP_THREADS_VALID, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "USEM: There are sleeping threads", + {NA, NA, 0, NA, NA, NA} }, + +/*line 141*/{(0x1F), 1, XSEM_REG_SLEEP_THREADS_VALID, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "XSEM: There are sleeping threads", + {NA, NA, 0, NA, NA, NA} }, + +/*line 142*/{(0x1F), 1, CSEM_REG_SLOW_EXT_STORE_EMPTY, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "CSEM: External store FIFO is not empty", + {NA, NA, 1, NA, NA, NA} }, + +/*line 143*/{(0x1F), 1, TSEM_REG_SLOW_EXT_STORE_EMPTY, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "TSEM: External store FIFO is not empty", + {NA, NA, 1, NA, NA, NA} }, + +/*line 144*/{(0x1F), 1, USEM_REG_SLOW_EXT_STORE_EMPTY, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "USEM: External store FIFO is not empty", + {NA, NA, 1, NA, NA, NA} }, + +/*line 145*/{(0x1F), 1, XSEM_REG_SLOW_EXT_STORE_EMPTY, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "XSEM: External store FIFO is not empty", + {NA, NA, 1, NA, NA, NA} }, + +/*line 146*/{(0x1F), 1, CSDM_REG_SYNC_PARSER_EMPTY, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "CSDM: Parser serial FIFO is not empty", + {NA, NA, 1, NA, NA, NA} }, + +/*line 147*/{(0x1F), 1, TSDM_REG_SYNC_PARSER_EMPTY, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "TSDM: Parser serial FIFO is not empty", + {NA, NA, 1, NA, NA, NA} }, + +/*line 148*/{(0x1F), 1, USDM_REG_SYNC_PARSER_EMPTY, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "USDM: Parser serial FIFO is not empty", + {NA, NA, 1, NA, NA, NA} }, + +/*line 149*/{(0x1F), 1, XSDM_REG_SYNC_PARSER_EMPTY, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "XSDM: Parser serial FIFO is not empty", + {NA, NA, 1, NA, NA, NA} }, + +/*line 150*/{(0x1F), 1, CSDM_REG_SYNC_SYNC_EMPTY, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "CSDM: Parser SYNC serial FIFO is not empty", + {NA, NA, 1, NA, NA, NA} }, + +/*line 151*/{(0x1F), 1, TSDM_REG_SYNC_SYNC_EMPTY, + NA, 1, 0, pneq, + NA, IDLE_CHK_ERROR_NO_TRAFFIC, + "TSDM: Parser SYNC serial FIFO is not empty", + {NA, NA, 1, NA, NA, NA} }, + +/*line 152*/{(0x1F), 1, USDM_REG_SYNC_SYNC_EMPTY, + NA, 1, 0, pneq, |