diff options
author | Ondrej Jirman <megous@megous.com> | 2019-12-19 09:28:20 -0800 |
---|---|---|
committer | Maxime Ripard <maxime@cerno.tech> | 2019-12-26 10:27:01 +0100 |
commit | b37da9c8e62ef8ea14c19d40837dcd5beb8470e6 (patch) | |
tree | e8a46db5e27f64cb0bb8bdc09e2bba8f86b5adae | |
parent | 1b084d2e4eaee9523c81824821b635fc90c0c6d8 (diff) |
ARM: dts: sun8i-h3: Add thermal sensor and thermal zones
There is just one sensor for the CPU.
Signed-off-by: Ondrej Jirman <megous@megous.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
-rw-r--r-- | arch/arm/boot/dts/sun8i-h3.dtsi | 20 | ||||
-rw-r--r-- | arch/arm/boot/dts/sunxi-h3-h5.dtsi | 6 |
2 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index b4f1673df9ee..20217e2ca4d3 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -208,6 +208,26 @@ assigned-clocks = <&ccu CLK_GPU>; assigned-clock-rates = <384000000>; }; + + ths: thermal-sensor@1c25000 { + compatible = "allwinner,sun8i-h3-ths"; + reg = <0x01c25000 0x400>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + resets = <&ccu RST_BUS_THS>; + clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; + clock-names = "bus", "mod"; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <0>; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 0>; + }; }; }; diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 0afea59486c2..6e68ed831015 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -231,6 +231,12 @@ sid: eeprom@1c14000 { /* compatible is in per SoC .dtsi file */ reg = <0x1c14000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + + ths_calibration: thermal-sensor-calibration@34 { + reg = <0x34 4>; + }; }; usb_otg: usb@1c19000 { |