diff options
author | Mike Frysinger <vapier@gentoo.org> | 2009-11-17 06:15:01 +0000 |
---|---|---|
committer | Mike Frysinger <vapier@gentoo.org> | 2009-12-15 00:16:16 -0500 |
commit | 31ad0e27ed71c30cd328b503ce6163392b4dd9e2 (patch) | |
tree | 6b0a3ef8380fd5f9d44f53c892e46b144e20ff0e | |
parent | b1740549d493d3ea5d16bee1cdc7b1f200163ad5 (diff) |
Blackfin: BF51x: unify def/cdef headers
Whole lot of duplicated code here just went bye bye.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
-rw-r--r-- | arch/blackfin/mach-bf518/include/mach/cdefBF514.h | 13 | ||||
-rw-r--r-- | arch/blackfin/mach-bf518/include/mach/cdefBF516.h | 80 | ||||
-rw-r--r-- | arch/blackfin/mach-bf518/include/mach/cdefBF518.h | 247 | ||||
-rw-r--r-- | arch/blackfin/mach-bf518/include/mach/defBF514.h | 45 | ||||
-rw-r--r-- | arch/blackfin/mach-bf518/include/mach/defBF516.h | 213 | ||||
-rw-r--r-- | arch/blackfin/mach-bf518/include/mach/defBF518.h | 592 |
6 files changed, 16 insertions, 1174 deletions
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF514.h b/arch/blackfin/mach-bf518/include/mach/cdefBF514.h index e1d99911025d..108fa4bde277 100644 --- a/arch/blackfin/mach-bf518/include/mach/cdefBF514.h +++ b/arch/blackfin/mach-bf518/include/mach/cdefBF514.h @@ -1,7 +1,7 @@ /* * Copyright 2008-2009 Analog Devices Inc. * - * Licensed under the GPL-2 or later + * Licensed under the ADI BSD license or the GPL-2 (or later) */ #ifndef _CDEF_BF514_H @@ -10,15 +10,8 @@ /* include all Core registers and bit definitions */ #include "defBF514.h" -/* include core specific register pointer definitions */ -#include <asm/cdef_LPBlackfin.h> - -/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF514 */ - -/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ -#include "cdefBF51x_base.h" - -/* The following are the #defines needed by ADSP-BF514 that are not in the common header */ +/* BF514 is BF512 + RSI */ +#include "cdefBF512.h" /* Removable Storage Interface Registers */ diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF516.h b/arch/blackfin/mach-bf518/include/mach/cdefBF516.h index 6b364eda4947..2751592ef1c1 100644 --- a/arch/blackfin/mach-bf518/include/mach/cdefBF516.h +++ b/arch/blackfin/mach-bf518/include/mach/cdefBF516.h @@ -1,7 +1,7 @@ /* * Copyright 2008-2009 Analog Devices Inc. * - * Licensed under the GPL-2 or later + * Licensed under the ADI BSD license or the GPL-2 (or later) */ #ifndef _CDEF_BF516_H @@ -10,15 +10,8 @@ /* include all Core registers and bit definitions */ #include "defBF516.h" -/* include core specific register pointer definitions */ -#include <asm/cdef_LPBlackfin.h> - -/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF516 */ - -/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ -#include "cdefBF51x_base.h" - -/* The following are the #defines needed by ADSP-BF516 that are not in the common header */ +/* BF516 is BF514 + EMAC */ +#include "cdefBF514.h" /* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ @@ -185,71 +178,4 @@ #define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT) #define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val) -/* Removable Storage Interface Registers */ - -#define bfin_read_RSI_PWR_CTL() bfin_read16(RSI_PWR_CONTROL) -#define bfin_write_RSI_PWR_CTL(val) bfin_write16(RSI_PWR_CONTROL, val) -#define bfin_read_RSI_CLK_CTL() bfin_read16(RSI_CLK_CONTROL) -#define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val) -#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT) -#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val) -#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND) -#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val) -#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD) -#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val) -#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0) -#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val) -#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1) -#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val) -#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2) -#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val) -#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3) -#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val) -#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER) -#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val) -#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH) -#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val) -#define bfin_read_RSI_DATA_CTL() bfin_read16(RSI_DATA_CONTROL) -#define bfin_write_RSI_DATA_CTL(val) bfin_write16(RSI_DATA_CONTROL, val) -#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT) -#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val) -#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS) -#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val) -#define bfin_read_RSI_STATUS_CLR() bfin_read16(RSI_STATUSCL) -#define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val) -#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0) -#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val) -#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1) -#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val) -#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT) -#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val) -#define bfin_read_RSI_CEATA_CTL() bfin_read16(RSI_CEATA_CONTROL) -#define bfin_write_RSI_CEATA_CTL(val) bfin_write16(RSI_CEATA_CONTROL, val) -#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO) -#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val) -#define bfin_read_RSI_E_STATUS() bfin_read16(RSI_ESTAT) -#define bfin_write_RSI_E_STATUS(val) bfin_write16(RSI_ESTAT, val) -#define bfin_read_RSI_E_MASK() bfin_read16(RSI_EMASK) -#define bfin_write_RSI_E_MASK(val) bfin_write16(RSI_EMASK, val) -#define bfin_read_RSI_CFG() bfin_read16(RSI_CONFIG) -#define bfin_write_RSI_CFG(val) bfin_write16(RSI_CONFIG, val) -#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN) -#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val) -#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0) -#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val) -#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1) -#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val) -#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2) -#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val) -#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3) -#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val) -#define bfin_read_RSI_PID4() bfin_read16(RSI_PID4) -#define bfin_write_RSI_PID4(val) bfin_write16(RSI_PID4, val) -#define bfin_read_RSI_PID5() bfin_read16(RSI_PID5) -#define bfin_write_RSI_PID5(val) bfin_write16(RSI_PID5, val) -#define bfin_read_RSI_PID6() bfin_read16(RSI_PID6) -#define bfin_write_RSI_PID6(val) bfin_write16(RSI_PID6, val) -#define bfin_read_RSI_PID7() bfin_read16(RSI_PID7) -#define bfin_write_RSI_PID7(val) bfin_write16(RSI_PID7, val) - #endif /* _CDEF_BF516_H */ diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF518.h b/arch/blackfin/mach-bf518/include/mach/cdefBF518.h index 929b90650bd4..7fb7f0eab990 100644 --- a/arch/blackfin/mach-bf518/include/mach/cdefBF518.h +++ b/arch/blackfin/mach-bf518/include/mach/cdefBF518.h @@ -1,7 +1,7 @@ /* * Copyright 2008-2009 Analog Devices Inc. * - * Licensed under the GPL-2 or later + * Licensed under the ADI BSD license or the GPL-2 (or later) */ #ifndef _CDEF_BF518_H @@ -10,181 +10,10 @@ /* include all Core registers and bit definitions */ #include "defBF518.h" -/* include core specific register pointer definitions */ -#include <asm/cdef_LPBlackfin.h> +/* BF518 is BF516 + IEEE-1588 */ +#include "cdefBF516.h" -/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF518 */ - -/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ -#include "cdefBF51x_base.h" - -/* The following are the #defines needed by ADSP-BF518 that are not in the common header */ - - -/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ - -#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE) -#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val) -#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO) -#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val) -#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI) -#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val) -#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO) -#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val) -#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI) -#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val) -#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD) -#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val) -#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT) -#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val) -#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC) -#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val) -#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1) -#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val) -#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2) -#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val) -#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL) -#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val) -#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0) -#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val) -#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1) -#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val) -#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2) -#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val) -#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3) -#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val) -#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD) -#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val) -#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF) -#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val) -#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0) -#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val) -#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1) -#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val) - -#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL) -#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val) -#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT) -#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val) -#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT) -#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val) -#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY) -#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val) -#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE) -#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val) -#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT) -#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val) -#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY) -#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val) -#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE) -#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val) - -#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL) -#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val) -#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS) -#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val) -#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE) -#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val) -#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS) -#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val) -#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE) -#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val) - -#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK) -#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val) -#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS) -#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val) -#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN) -#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val) -#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET) -#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val) -#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF) -#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val) -#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST) -#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val) -#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI) -#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val) -#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD) -#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val) -#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI) -#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val) -#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO) -#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val) -#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG) -#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val) -#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL) -#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val) -#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE) -#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val) -#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE) -#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val) -#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM) -#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val) -#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT) -#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val) -#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED) -#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val) -#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT) -#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val) -#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64) -#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val) -#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128) -#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val) -#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256) -#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val) -#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512) -#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val) -#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024) -#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val) -#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024) -#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val) - -#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK) -#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val) -#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL) -#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val) -#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL) -#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val) -#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET) -#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val) -#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER) -#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val) -#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL) -#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val) -#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL) -#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val) -#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND) -#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val) -#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR) -#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val) -#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST) -#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val) -#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI) -#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val) -#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD) -#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val) -#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR) -#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val) -#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL) -#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val) -#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM) -#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val) -#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT) -#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val) -#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64) -#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val) -#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128) -#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val) -#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256) -#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val) -#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512) -#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val) -#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024) -#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val) -#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024) -#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val) -#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT) -#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val) +/* PTP TSYNC Registers */ #define bfin_read_EMAC_PTP_CTL() bfin_read16(EMAC_PTP_CTL) #define bfin_write_EMAC_PTP_CTL(val) bfin_write16(EMAC_PTP_CTL, val) @@ -227,72 +56,4 @@ #define bfin_read_EMAC_PTP_PPS_PERIOD() bfin_read32(EMAC_PTP_PPS_PERIOD) #define bfin_write_EMAC_PTP_PPS_PERIOD(val) bfin_write32(EMAC_PTP_PPS_PERIOD, val) -/* Removable Storage Interface Registers */ - -#define bfin_read_RSI_PWR_CTL() bfin_read16(RSI_PWR_CONTROL) -#define bfin_write_RSI_PWR_CTL(val) bfin_write16(RSI_PWR_CONTROL, val) -#define bfin_read_RSI_CLK_CTL() bfin_read16(RSI_CLK_CONTROL) -#define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val) -#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT) -#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val) -#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND) -#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val) -#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD) -#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val) -#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0) -#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val) -#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1) -#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val) -#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2) -#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val) -#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3) -#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val) -#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER) -#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val) -#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH) -#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val) -#define bfin_read_RSI_DATA_CTL() bfin_read16(RSI_DATA_CONTROL) -#define bfin_write_RSI_DATA_CTL(val) bfin_write16(RSI_DATA_CONTROL, val) -#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT) -#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val) -#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS) -#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val) -#define bfin_read_RSI_STATUS_CLR() bfin_read16(RSI_STATUSCL) -#define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val) -#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0) -#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val) -#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1) -#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val) -#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT) -#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val) -#define bfin_read_RSI_CEATA_CTL() bfin_read16(RSI_CEATA_CONTROL) -#define bfin_write_RSI_CEATA_CTL(val) bfin_write16(RSI_CEATA_CONTROL, val) -#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO) -#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val) -#define bfin_read_RSI_E_STATUS() bfin_read16(RSI_ESTAT) -#define bfin_write_RSI_E_STATUS(val) bfin_write16(RSI_ESTAT, val) -#define bfin_read_RSI_E_MASK() bfin_read16(RSI_EMASK) -#define bfin_write_RSI_E_MASK(val) bfin_write16(RSI_EMASK, val) -#define bfin_read_RSI_CFG() bfin_read16(RSI_CONFIG) -#define bfin_write_RSI_CFG(val) bfin_write16(RSI_CONFIG, val) -#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN) -#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val) -#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0) -#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val) -#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1) -#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val) -#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2) -#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val) -#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3) -#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val) -#define bfin_read_RSI_PID4() bfin_read16(RSI_PID4) -#define bfin_write_RSI_PID4(val) bfin_write16(RSI_PID4, val) -#define bfin_read_RSI_PID5() bfin_read16(RSI_PID5) -#define bfin_write_RSI_PID5(val) bfin_write16(RSI_PID5, val) -#define bfin_read_RSI_PID6() bfin_read16(RSI_PID6) -#define bfin_write_RSI_PID6(val) bfin_write16(RSI_PID6, val) -#define bfin_read_RSI_PID7() bfin_read16(RSI_PID7) -#define bfin_write_RSI_PID7(val) bfin_write16(RSI_PID7, val) - - #endif /* _CDEF_BF518_H */ diff --git a/arch/blackfin/mach-bf518/include/mach/defBF514.h b/arch/blackfin/mach-bf518/include/mach/defBF514.h index b5adca23a788..92e950d6e996 100644 --- a/arch/blackfin/mach-bf518/include/mach/defBF514.h +++ b/arch/blackfin/mach-bf518/include/mach/defBF514.h @@ -7,49 +7,8 @@ #ifndef _DEF_BF514_H #define _DEF_BF514_H -/* Include all Core registers and bit definitions */ -#include <asm/def_LPBlackfin.h> - -/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF514 */ - -/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ -#include "defBF51x_base.h" - -/* The following are the #defines needed by ADSP-BF514 that are not in the common header */ - -/* SDH Registers */ - -#define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */ -#define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */ -#define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */ -#define SDH_COMMAND 0xFFC0390C /* SDH Command */ -#define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */ -#define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */ -#define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */ -#define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */ -#define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */ -#define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */ -#define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */ -#define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */ -#define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */ -#define SDH_STATUS 0xFFC03934 /* SDH Status */ -#define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */ -#define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */ -#define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */ -#define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */ -#define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */ -#define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */ -#define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */ -#define SDH_CFG 0xFFC039C8 /* SDH Configuration */ -#define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */ -#define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */ -#define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */ -#define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */ -#define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */ -#define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */ -#define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */ -#define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */ -#define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */ +/* BF514 is BF512 + RSI */ +#include "defBF512.h" /* Removable Storage Interface Registers */ diff --git a/arch/blackfin/mach-bf518/include/mach/defBF516.h b/arch/blackfin/mach-bf518/include/mach/defBF516.h index 7eb18774d727..22a3aa0d2629 100644 --- a/arch/blackfin/mach-bf518/include/mach/defBF516.h +++ b/arch/blackfin/mach-bf518/include/mach/defBF516.h @@ -7,13 +7,8 @@ #ifndef _DEF_BF516_H #define _DEF_BF516_H -/* Include all Core registers and bit definitions */ -#include <asm/def_LPBlackfin.h> - -/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF516 */ - -/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ -#include "defBF51x_base.h" +/* BF516 is BF514 + EMAC */ +#include "defBF514.h" /* The following are the #defines needed by ADSP-BF516 that are not in the common header */ /* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ @@ -394,208 +389,4 @@ #define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */ #define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */ -/* SDH Registers */ - -#define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */ -#define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */ -#define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */ -#define SDH_COMMAND 0xFFC0390C /* SDH Command */ -#define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */ -#define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */ -#define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */ -#define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */ -#define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */ -#define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */ -#define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */ -#define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */ -#define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */ -#define SDH_STATUS 0xFFC03934 /* SDH Status */ -#define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */ -#define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */ -#define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */ -#define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */ -#define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */ -#define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */ -#define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */ -#define SDH_CFG 0xFFC039C8 /* SDH Configuration */ -#define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */ -#define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */ -#define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */ -#define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */ -#define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */ -#define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */ -#define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */ -#define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */ -#define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */ - -/* Removable Storage Interface Registers */ - -#define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */ -#define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */ -#define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */ -#define RSI_COMMAND 0xFFC0380C /* RSI Command Register */ -#define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */ -#define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */ -#define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */ -#define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */ -#define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */ -#define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */ -#define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */ -#define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */ -#define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */ -#define RSI_STATUS 0xFFC03834 /* RSI Status Register */ -#define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */ -#define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */ -#define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */ -#define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */ -#define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */ -#define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */ -#define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */ -#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */ -#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */ -#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */ -#define RSI_PID0 0xFFC03FE0 /* RSI Peripheral ID Register 0 */ -#define RSI_PID1 0xFFC03FE4 /* RSI Peripheral ID Register 1 */ -#define RSI_PID2 0xFFC03FE8 /* RSI Peripheral ID Register 2 */ -#define RSI_PID3 0xFFC03FEC /* RSI Peripheral ID Register 3 */ -#define RSI_PID4 0xFFC03FF0 /* RSI Peripheral ID Register 4 */ -#define RSI_PID5 0xFFC03FF4 /* RSI Peripheral ID Register 5 */ -#define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */ -#define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */ - -/* ********************************************************** */ -/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */ -/* and MULTI BIT READ MACROS */ -/* ********************************************************** */ - -/* Bit masks for SDH_COMMAND */ - -#define CMD_IDX 0x3f /* Command Index */ -#define CMD_RSP 0x40 /* Response */ -#define CMD_L_RSP 0x80 /* Long Response */ -#define CMD_INT_E 0x100 /* Command Interrupt */ -#define CMD_PEND_E 0x200 /* Command Pending */ -#define CMD_E 0x400 /* Command Enable */ - -/* Bit masks for SDH_PWR_CTL */ - -#define PWR_ON 0x3 /* Power On */ -#if 0 -#define TBD 0x3c /* TBD */ -#endif -#define SD_CMD_OD 0x40 /* Open Drain Output */ -#define ROD_CTL 0x80 /* Rod Control */ - -/* Bit masks for SDH_CLK_CTL */ - -#define CLKDIV 0xff /* MC_CLK Divisor */ -#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ -#define PWR_SV_E 0x200 /* Power Save Enable */ -#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ -#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ - -/* Bit masks for SDH_RESP_CMD */ - -#define RESP_CMD 0x3f /* Response Command */ - -/* Bit masks for SDH_DATA_CTL */ - -#define DTX_E 0x1 /* Data Transfer Enable */ -#define DTX_DIR 0x2 /* Data Transfer Direction */ -#define DTX_MODE 0x4 /* Data Transfer Mode */ -#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ -#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ - -/* Bit masks for SDH_STATUS */ - -#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ -#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ -#define CMD_TIME_OUT 0x4 /* CMD Time Out */ -#define DAT_TIME_OUT 0x8 /* Data Time Out */ -#define TX_UNDERRUN 0x10 /* Transmit Underrun */ -#define RX_OVERRUN 0x20 /* Receive Overrun */ -#define CMD_RESP_END 0x40 /* CMD Response End */ -#define CMD_SENT 0x80 /* CMD Sent */ -#define DAT_END 0x100 /* Data End */ -#define START_BIT_ERR 0x200 /* Start Bit Error */ -#define DAT_BLK_END 0x400 /* Data Block End */ -#define CMD_ACT 0x800 /* CMD Active */ -#define TX_ACT 0x1000 /* Transmit Active */ -#define RX_ACT 0x2000 /* Receive Active */ -#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ -#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ -#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ -#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ -#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ -#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ -#define TX_DAT_RDY 0x100000 /* Transmit Data Available */ -#define RX_FIFO_RDY 0x200000 /* Receive Data Available */ - -/* Bit masks for SDH_STATUS_CLR */ - -#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ -#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ -#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ -#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ -#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ -#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ -#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ -#define CMD_SENT_STAT 0x80 /* CMD Sent Status */ -#define DAT_END_STAT 0x100 /* Data End Status */ -#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ -#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ - -/* Bit masks for SDH_MASK0 */ - -#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ -#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ -#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ -#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ -#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ -#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ -#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ -#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ -#define DAT_END_MASK 0x100 /* Data End Mask */ -#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ -#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ -#define CMD_ACT_MASK 0x800 /* CMD Active Mask */ -#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ -#define RX_ACT_MASK 0x2000 /* Receive Active Mask */ -#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ -#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ -#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ -#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ -#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ -#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ -#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ -#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ - -/* Bit masks for SDH_FIFO_CNT */ - -#define FIFO_COUNT 0x7fff /* FIFO Count */ - -/* Bit masks for SDH_E_STATUS */ - -#define SDIO_INT_DET 0x2 /* SDIO Int Detected */ -#define SD_CARD_DET 0x10 /* SD Card Detect */ - -/* Bit masks for SDH_E_MASK */ - -#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ -#define SCD_MSK 0x40 /* Mask Card Detect */ - -/* Bit masks for SDH_CFG */ - -#define CLKS_EN 0x1 /* Clocks Enable */ -#define SD4E 0x4 /* SDIO 4-Bit Enable */ -#define MWE 0x8 /* Moving Window Enable */ -#define SD_RST 0x10 /* SDMMC Reset */ -#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ -#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ -#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ - -/* Bit masks for SDH_RD_WAIT_EN */ - -#define RWR 0x1 /* Read Wait Request */ - #endif /* _DEF_BF516_H */ diff --git a/arch/blackfin/mach-bf518/include/mach/defBF518.h b/arch/blackfin/mach-bf518/include/mach/defBF518.h index 794cf06eb5ba..cb18270e55c2 100644 --- a/arch/blackfin/mach-bf518/include/mach/defBF518.h +++ b/arch/blackfin/mach-bf518/include/mach/defBF518.h @@ -7,461 +7,8 @@ #ifndef _DEF_BF518_H #define _DEF_BF518_H -/* Include all Core registers and bit definitions */ -#include <asm/def_LPBlackfin.h> - -/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF518 */ - -/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */ -#include "defBF51x_base.h" |