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-rw-r--r--Makefile10
-rw-r--r--README.md34
-rw-r--r--aarch64/corefreq-cli.c35
-rw-r--r--aarch64/corefreq-ui.c18
-rw-r--r--aarch64/corefreq-ui.h2
-rw-r--r--aarch64/corefreqd.c2
-rw-r--r--aarch64/corefreqk.c24
-rw-r--r--aarch64/coretypes.h4
-rw-r--r--ckms.ini2
-rw-r--r--dkms.conf2
-rw-r--r--x86_64/corefreq-api.h43
-rw-r--r--x86_64/corefreq-cli-json.c31
-rw-r--r--x86_64/corefreq-cli-rsc-en.h13
-rw-r--r--x86_64/corefreq-cli-rsc-fr.h18
-rw-r--r--x86_64/corefreq-cli-rsc.c11
-rw-r--r--x86_64/corefreq-cli-rsc.h11
-rw-r--r--x86_64/corefreq-cli.c142
-rw-r--r--x86_64/corefreq-ui.c18
-rw-r--r--x86_64/corefreq-ui.h2
-rw-r--r--x86_64/corefreq.h12
-rw-r--r--x86_64/corefreqd.c401
-rw-r--r--x86_64/corefreqk.c332
-rw-r--r--x86_64/corefreqk.h30
-rw-r--r--x86_64/coretypes.h18
-rw-r--r--x86_64/intel_reg.h311
25 files changed, 1425 insertions, 101 deletions
diff --git a/Makefile b/Makefile
index a21614a..c0b7946 100644
--- a/Makefile
+++ b/Makefile
@@ -97,6 +97,14 @@ ifneq ($(UI_TRANSPARENCY),)
LAYOUT += -D UI_TRANSPARENCY=$(UI_TRANSPARENCY)
endif
+ifneq ($(UI_RULER_MINIMUM),)
+LAYOUT += -D UI_RULER_MINIMUM=$(UI_RULER_MINIMUM)
+endif
+
+ifneq ($(UI_RULER_MAXIMUM),)
+LAYOUT += -D UI_RULER_MAXIMUM=$(UI_RULER_MAXIMUM)
+endif
+
.PHONY: all
all: prepare corefreqd corefreq-cli | prepare
@if [ -e $(BUILD)/Makefile ]; then \
@@ -332,6 +340,8 @@ help:
"| when <F> is 1: don't build and display this area part |\n"\
"| UI_TRANSPARENCY=<F> |\n"\
"| when <F> is 1: build with background transparency |\n"\
+ "| UI_RULER_MINIMUM=<N>, UI_RULER_MAXIMUM=<N> |\n"\
+ "| set ruler left or right bound to <N> frequency ratio |\n"\
"| |\n"\
"| Example: |\n"\
"| make CC=gcc OPTIM_LVL=3 FEAT_DBG=1 ARCH_PMC=PCU |\n"\
diff --git a/README.md b/README.md
index 47147cc..21311dd 100644
--- a/README.md
+++ b/README.md
@@ -71,6 +71,7 @@ Uncomment and set `draw_bold_text_with_bright_colors: true` in `<config-file>`
* Linux Kernel Header files to build modules
* Mandatory : `CONFIG_MODULES, CONFIG_SMP, CONFIG_X86_MSR`
* Optionally: `CONFIG_HOTPLUG_CPU, CONFIG_CPU_IDLE, CONFIG_CPU_FREQ, CONFIG_PM_SLEEP, CONFIG_DMI, CONFIG_HAVE_NMI, CONFIG_XEN, CONFIG_AMD_NB, CONFIG_SCHED_MUQSS, CONFIG_SCHED_BMQ, CONFIG_SCHED_PDS, CONFIG_SCHED_ALT, CONFIG_SCHED_BORE, CONFIG_CACHY, CONFIG_ACPI, CONFIG_ACPI_CPPC_LIB`
+ * Forbidden : `CONFIG_TRIM_UNUSED_KSYMS`
2. Clone the source code into a working directory.
```sh
@@ -255,13 +256,42 @@ apt install dkms
apt list git build-essential gawk fakeroot linux-headers*
```
-## Red Hat, CentOS, AlmaLinux
+## Red Hat, CentOS
* Development packages prerequisites.
```sh
yum install kernel-devel
yum group install "Development Tools"
```
+## AlmaLinux
+```sh
+## as root, install kernel development package and dependencies
+dnf --assumeyes install kernel-devel gcc make git bc
+```
+```sh
+## as a User, build CoreFreq
+cd CoreFreq
+make -j
+```
+```sh
+## as root, install the binaries
+make install
+## and start Driver and Daemon
+modprobe corefreqk
+corefreqd
+```
+```sh
+## as a User, start the Client
+corefreq-cli
+```
+```sh
+## Terminate Client, Daemon and unload Driver as root
+modprobe -r corefreqk
+## Proceed to uninstallation as root
+cd CoreFreq
+make uninstall
+```
+
## openSUSE
* Packages
1. [CoreFreq](https://software.opensuse.org/package/CoreFreq) official release
@@ -557,6 +587,8 @@ o---------------------------------------------------------------o
| when <F> is 1: don't build and display this area part |
| UI_TRANSPARENCY=<F> |
| when <F> is 1: build with background transparency |
+| UI_RULER_MINIMUM=<N>, UI_RULER_MAXIMUM=<N> |
+| set ruler left or right bound to <N> frequency ratio |
| |
| Example: |
| make CC=gcc OPTIM_LVL=3 FEAT_DBG=1 ARCH_PMC=PCU |
diff --git a/aarch64/corefreq-cli.c b/aarch64/corefreq-cli.c
index bd057aa..6450016 100644
--- a/aarch64/corefreq-cli.c
+++ b/aarch64/corefreq-cli.c
@@ -216,12 +216,33 @@ void AggregateRatio(void)
}
InsertionSortRuler(Ruler.Uniq, Ruler.Count, BOOST(MIN));
+ #ifndef UI_RULER_MINIMUM
Ruler.Minimum = (double) lowest;
+ #elif (UI_RULER_MINIMUM > 0) && (UI_RULER_MINIMUM <= MAX_WIDTH)
+ Ruler.Minimum = (double) UI_RULER_MINIMUM;
+ #else
+ Ruler.Minimum = 1.0;
+ #endif
+ #ifndef UI_RULER_MAXIMUM
Ruler.Maximum = (double) highest;
- Ruler.Median = (double) RO(Shm)->Cpu[
- Ruler.Top[BOOST(ACT)]
- ].Boost[BOOST(ACT)];
+ #elif (UI_RULER_MAXIMUM > 0) && (UI_RULER_MAXIMUM <= MAX_WIDTH)
+ Ruler.Maximum = (double) UI_RULER_MAXIMUM;
+ #else
+ Ruler.Maximum = (double) MIN_WIDTH;
+ #endif
+ #if !defined(UI_RULER_MINIMUM) && !defined(UI_RULER_MAXIMUM)
+ {
+ const double median = (double) RO(Shm)->Cpu[
+ Ruler.Top[BOOST(ACT)]
+ ].Boost[BOOST(ACT)];
+ if ((median > Ruler.Minimum) && (median < Ruler.Maximum)) {
+ Ruler.Median = median;
+ }
+ }
+ #else
+ Ruler.Median = 0.0;
+ #endif
if (Ruler.Median == 0.0) {
Ruler.Median = (Ruler.Minimum + Ruler.Maximum) / 2.0;
}
@@ -13143,8 +13164,10 @@ void Layout_Ruler_Load(Layer *layer, CUINT row)
/* Alternate the color of the frequency ratios */
while (idx--)
- {
- double fPos = (Ruler.Uniq[idx] * Draw.Area.LoadWidth) / Ruler.Maximum;
+ if (Ruler.Uniq[idx] <= Ruler.Maximum)
+ {
+ const double fPos = (Ruler.Uniq[idx] * Draw.Area.LoadWidth)
+ / Ruler.Maximum;
CUINT hPos = (CUINT) fPos;
ASCII tabStop[10+1] = "00";
@@ -13161,7 +13184,7 @@ void Layout_Ruler_Load(Layer *layer, CUINT row)
bright = !bright;
}
lPos = hPos >= margin ? hPos - margin : margin;
- }
+ }
LayerCopyAt(layer, hLoad1.origin.col, hLoad1.origin.row, hLoad1.length,
hLoad1.attr[Draw.Load], hLoad1.code[Draw.Load]);
}
diff --git a/aarch64/corefreq-ui.c b/aarch64/corefreq-ui.c
index 34e40c0..0d67fc4 100644
--- a/aarch64/corefreq-ui.c
+++ b/aarch64/corefreq-ui.c
@@ -608,13 +608,21 @@ int GetKey(SCANKEY *scan, struct timespec *tsec)
SCREEN_SIZE GetScreenSize(void)
{
- SCREEN_SIZE _screenSize = {.width = 0, .height = 0};
- struct winsize ts;
+ SCREEN_SIZE _screenSize = {.width = MIN_WIDTH, .height = MIN_HEIGHT};
- ioctl(STDIN_FILENO, TIOCGWINSZ, &ts);
- _screenSize.width = (int) ts.ws_col;
- _screenSize.height = (int) ts.ws_row;
+#if defined(TIOCGWINSZ)
+ struct winsize ts;
+ if (ioctl(STDIN_FILENO, TIOCGWINSZ, &ts) >= 0) {
+ const int _col = (int) ts.ws_col, _row = (int) ts.ws_row;
+ if (_col > 0) {
+ _screenSize.width = _col;
+ }
+ if (_row > 0) {
+ _screenSize.height = _row;
+ }
+ }
+#endif
return _screenSize;
}
diff --git a/aarch64/corefreq-ui.h b/aarch64/corefreq-ui.h
index 0cc91e6..91dac2a 100644
--- a/aarch64/corefreq-ui.h
+++ b/aarch64/corefreq-ui.h
@@ -35,6 +35,8 @@
+ 3 /* SEPARATOR */ \
+ 2 /* FOOTER_ROW */)
+#define MIN_HEIGHT 24
+
#define MAX_WIDTH 320
#define MIN_WIDTH 80
diff --git a/aarch64/corefreqd.c b/aarch64/corefreqd.c
index 3c739e6..95ab2fe 100644
--- a/aarch64/corefreqd.c
+++ b/aarch64/corefreqd.c
@@ -475,7 +475,7 @@ static void *Child_Thread(void *arg)
CALL_FUNC CallSliceFunc = (CALL_FUNC[2]){
CallWith_RDTSC_No_RDPMC, CallWith_RDTSC_RDPMC
- }[ RO(Shm)->Proc.Features.PerfMon.FixCtrs == 2 ];
+ }[ RO(Shm)->Proc.Features.PerfMon.CoreCycles > 0 ];
pthread_t tid = pthread_self();
cpu_set_t cpuset;
diff --git a/aarch64/corefreqk.c b/aarch64/corefreqk.c
index 536b982..37dd210 100644
--- a/aarch64/corefreqk.c
+++ b/aarch64/corefreqk.c
@@ -586,7 +586,6 @@ static void Query_Features(void *pArg)
iArg->Features->PerfMon.Version = dfr0.PMUVer;
if (iArg->Features->PerfMon.Version > 0) {
iArg->Features->PerfMon.FixCtrs++; /* Fixed Cycle Counter */
- iArg->Features->PerfMon.FixCtrs++; /* Instruction Counter */
}
/*TODO(Memory-mapped PMU register at offset 0xe00): pmcfgr */
iArg->Features->PerfMon.MonWidth = \
@@ -2532,6 +2531,8 @@ static void PerCore_GenericMachine(void *arg)
{
volatile CPUPWRCTLR cpuPwrCtl;
volatile PMUSERENR pmuser;
+ volatile PMCNTENSET enset;
+ volatile PMCNTENCLR enclr;
volatile REVIDR revid;
CORE_RO *Core = (CORE_RO *) arg;
@@ -2548,15 +2549,23 @@ static void PerCore_GenericMachine(void *arg)
}
__asm__ __volatile__(
"mrs %[pmuser], pmuserenr_el0" "\n\t"
+ "mrs %[enset], pmcntenset_el0" "\n\t"
+ "mrs %[enclr], pmcntenclr_el0" "\n\t"
"isb"
- : [pmuser] "=r" (pmuser)
+ : [pmuser] "=r" (pmuser),
+ [enset] "=r" (enset),
+ [enclr] "=r" (enclr)
:
: "memory"
);
if (Core->Bind == PUBLIC(RO(Proc))->Service.Core) {
- PUBLIC(RO(Proc))->Features.PerfMon.CoreCycles = pmuser.CR;
- PUBLIC(RO(Proc))->Features.PerfMon.InstrRetired = pmuser.IR;
+ PUBLIC(RO(Proc))->Features.PerfMon.CoreCycles = pmuser.CR
+ | enset.C
+ | enclr.C;
+ PUBLIC(RO(Proc))->Features.PerfMon.InstrRetired = pmuser.IR
+ | enset.F0
+ | enclr.F0;
}
__asm__ __volatile__(
"mrs %[revid], revidr_el1" "\n\t"
@@ -3896,7 +3905,8 @@ static int CoreFreqK_FreqDriver_UnInit(void)
{
int rc = -EINVAL;
#ifdef CONFIG_CPU_FREQ
-#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 3, 0)) && (!defined(CONFIG_CACHY))
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(6, 3, 0)) && (!defined(CONFIG_CACHY)) \
+ && (!defined(RHEL_MAJOR))
rc =
#else
rc = 0;
@@ -5348,7 +5358,7 @@ inline void SMBIOS_Decoder(void)
#endif /* CONFIG_DMI */
}
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 2, 0)
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 2, 0) || (RHEL_MAJOR >= 9)
static char *CoreFreqK_DevNode(const struct device *dev, umode_t *mode)
#else
static char *CoreFreqK_DevNode(struct device *dev, umode_t *mode)
@@ -5492,7 +5502,7 @@ static int CoreFreqK_Create_Device_Level_Up(INIT_ARG *pArg)
struct device *tmpDev;
UNUSED(pArg);
-#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 4, 0)
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 4, 0) || (RHEL_MAJOR >= 9)
CoreFreqK.clsdev = class_create(DRV_DEVNAME);
#else
CoreFreqK.clsdev = class_create(THIS_MODULE, DRV_DEVNAME);
diff --git a/aarch64/coretypes.h b/aarch64/coretypes.h
index 3fcf0de..303fa28 100644
--- a/aarch64/coretypes.h
+++ b/aarch64/coretypes.h
@@ -5,8 +5,8 @@
*/
#define COREFREQ_MAJOR 1
-#define COREFREQ_MINOR 97
-#define COREFREQ_REV 1
+#define COREFREQ_MINOR 98
+#define COREFREQ_REV 0
#if !defined(CORE_COUNT)
#define CORE_COUNT 256
diff --git a/ckms.ini b/ckms.ini
index 9bcfb86..08f75b3 100644
--- a/ckms.ini
+++ b/ckms.ini
@@ -6,7 +6,7 @@
#
[general]
name = corefreqk
-version = 1.97
+version = 1.98
strip = yes
make = gmake
initramfs = no
diff --git a/dkms.conf b/dkms.conf
index d4db8e5..0cb7fa2 100644
--- a/dkms.conf
+++ b/dkms.conf
@@ -5,7 +5,7 @@
AUTOINSTALL="yes"
## REMAKE_INITRD="no"
DRV_PATH=/updates
-DRV_VERSION=1.97
+DRV_VERSION=1.98
PACKAGE_NAME="corefreqk"
PACKAGE_VERSION="$DRV_VERSION"
BUILT_MODULE_NAME[0]="corefreqk"
diff --git a/x86_64/corefreq-api.h b/x86_64/corefreq-api.h
index 9502aff..bcceefd 100644
--- a/x86_64/corefreq-api.h
+++ b/x86_64/corefreq-api.h
@@ -599,6 +599,19 @@ typedef struct
/* E4C0h */ ADL_IMC_SREXITTP SRExit; /* 64 bits */
} ADL;
struct {
+ /* E000h */ MTL_IMC_CR_TC_PRE Timing; /* 64 bits */
+ /* E138h */ MTL_IMC_CR_TC_ACT ACT; /* 64 bits */
+ /* E00Ch */ MTL_IMC_CR_TC_RDRD RDRD; /* 32 bits */
+ /* E010h */ MTL_IMC_CR_TC_RDWR RDWR; /* 32 bits */
+ /* E014h */ MTL_IMC_CR_TC_WRRD WRRD; /* 32 bits */
+ /* E018h */ MTL_IMC_CR_TC_WRWR WRWR; /* 32 bits */
+ /* E050h */ MTL_IMC_TC_PWDEN PWDEN; /* 64-bits */
+ /* E070h */ MTL_IMC_CR_TC_ODT ODT; /* 64 bits */
+ /* E088h */ MTL_IMC_SC_GS_CFG Sched; /* 64 bits */
+ /* E4A0h */ MTL_IMC_REFRESH_TC Refresh; /*64 bits */
+ /* E4C0h */ MTL_IMC_SREXITTP SRExit; /* 64 bits */
+ } MTL;
+ struct {
/* 88h */ AMD_0F_DRAM_TIMING_LOW DTRL; /* 32 bits */
} AMD0Fh;
struct
@@ -730,6 +743,13 @@ typedef struct
/* D810h */ MADD1; /* 32 bits */
} ADL;
struct {
+ /* D800h */ MTL_IMC_MAD_MAPPING MADCH; /* 32 bits */
+ /* D804h */ MTL_IMC_MAD_CHANNEL MADC0, /* 32 bits */
+ /* D808h */ MADC1; /* 32 bits */
+ /* D80Ch */ MTL_IMC_MAD_DIMM MADD0, /* 32 bits */
+ /* D810h */ MADD1; /* 32 bits */
+ } MTL;
+ struct {
/* 90h */ AMD_0F_DRAM_CONFIG_LOW DCRL; /* 32 bits */
/* 94h */ AMD_0F_DRAM_CONFIG_HIGH DCRH; /* 32 bits */
} AMD0Fh;
@@ -794,8 +814,15 @@ typedef struct
ADL_SA_PERF_STATUS ADL_SA_Pll;
};
struct {
- GKL_CAPID_A GKL_Cap_A;
- GKL_CAPID_B GKL_Cap_B;
+ GLK_CAPID_A GLK_Cap_A;
+ GLK_CAPID_B GLK_Cap_B;
+ };
+ struct {
+ MTL_CAPID_A MTL_Cap_A;
+ MTL_CAPID_B MTL_Cap_B;
+ MTL_CAPID_C MTL_Cap_C;
+ MTL_CAPID_E MTL_Cap_E;
+ MTL_SA_PERF_STATUS MTL_SA_Pll;
};
struct {
AMD_0F_HTT_NODE_ID NodeID;
@@ -1479,9 +1506,15 @@ typedef struct
#define DID_INTEL_RAPTORLAKE_B760_PCH 0x7a06
/* Source: Intel(R) Pentium(R) Silver N5000 CPU @ 1.10GHz */
#define DID_INTEL_GEMINILAKE_HB 0x31f0
-/* Source: Meteor Lake kernel preview: Intel(R) Core(TM) Ultra 7 1003H */
-#define DID_INTEL_METEORLAKE_M_6_8_2_HB 0x7d01
-#define DID_INTEL_METEORLAKE_PCH 0x7e02
+/* Source: Meteor Lake: Intel Core Ultra Processor Datasheet, Vol 1 */
+#define DID_INTEL_METEORLAKE_UT4_2_8_2_HB 0x7d00
+#define DID_INTEL_METEORLAKE_H_6_8_2_HB 0x7d01
+#define DID_INTEL_METEORLAKE_U_2_8_2_HB 0x7d02
+#define DID_INTEL_METEORLAKE_H_4_8_2_HB 0x7d14
+#define DID_INTEL_METEORLAKE_U_2_4_2_HB 0x7d16
+#define DID_INTEL_METEORLAKE_H_PCH 0x7e02
+#define DID_INTEL_METEORLAKE_U_PCH 0x7e03
+#define DID_INTEL_METEORLAKE_UT4_PCH 0x7e07
/* Source: /include/linux/pci_ids.h */
#define DID_AMD_K8_NB_MEMCTL 0x1102
#define DID_AMD_K8_NB 0x1100
diff --git a/x86_64/corefreq-cli-json.c b/x86_64/corefreq-cli-json.c
index f6a7de7..c7ebe1a 100644
--- a/x86_64/corefreq-cli-json.c
+++ b/x86_64/corefreq-cli-json.c
@@ -1400,9 +1400,20 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm))
}
json_end_object(&s);
}
- json_key(&s, "FactoryFreq");
- json_literal(&s, "%u", RO(Shm)->Proc.Features.Factory.Freq);
+ json_key(&s, "Factory");
+ {
+ json_start_object(&s);
+ json_key(&s, "Freq");
+ json_literal(&s, "%u", RO(Shm)->Proc.Features.Factory.Freq);
+ json_key(&s, "Ratio");
+ json_literal(&s, "%u", RO(Shm)->Proc.Features.Factory.Ratio);
+ json_key(&s, "Bins");
+ json_literal(&s, "%u", RO(Shm)->Proc.Features.Factory.Bins);
+ json_key(&s, "Overclock");
+ json_literal(&s, "%u", RO(Shm)->Proc.Features.Factory.Overclock);
+ json_end_object(&s);
+ }
json_key(&s, "InvariantTSC");
json_literal(&s, "%u", RO(Shm)->Proc.Features.InvariantTSC);
json_key(&s, "HyperThreading");
@@ -1449,6 +1460,10 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm))
json_literal(&s, "%u", RO(Shm)->Proc.Features.SpecTurboRatio);
json_key(&s, "XtraCOF");
json_literal(&s, "%u", RO(Shm)->Proc.Features.XtraCOF);
+ json_key(&s, "OC_Enable");
+ json_literal(&s, "%u", RO(Shm)->Proc.Features.OC_Enable);
+ json_key(&s, "OC_Lock");
+ json_literal(&s, "%u", RO(Shm)->Proc.Features.OC_Lock);
json_end_object(&s);
}
@@ -1531,6 +1546,18 @@ void JsonSysInfo(RO(SHM_STRUCT) *RO(Shm))
json_literal(&s, "%llu", RO(Shm)->Proc.Technology.L2_UpDown_Pf);
json_key(&s, "LLC_Streamer");
json_literal(&s, "%llu", RO(Shm)->Proc.Technology.LLC_Streamer);
+ json_key(&s, "VMD");
+ json_literal(&s, "%llu", RO(Shm)->Proc.Technology.VMD);
+ json_key(&s, "GNA");
+ json_literal(&s, "%llu", RO(Shm)->Proc.Technology.GNA);
+ json_key(&s, "HDCP");
+ json_literal(&s, "%llu", RO(Shm)->Proc.Technology.HDCP);
+ json_key(&s, "IPU");
+ json_literal(&s, "%llu", RO(Shm)->Proc.Technology.IPU);
+ json_key(&s, "VPU");
+ json_literal(&s, "%llu", RO(Shm)->Proc.Technology.VPU);
+ json_key(&s, "OC");
+ json_literal(&s, "%llu", RO(Shm)->Proc.Technology.OC);
json_end_object(&s);
}
diff --git a/x86_64/corefreq-cli-rsc-en.h b/x86_64/corefreq-cli-rsc-en.h
index 81d107a..5561fdb 100644
--- a/x86_64/corefreq-cli-rsc-en.h
+++ b/x86_64/corefreq-cli-rsc-en.h
@@ -854,6 +854,8 @@
#define RSC_FREQUENCY_CODE_EN "Frequency"
#define RSC_RATIO_CODE_EN "Ratio"
#define RSC_FACTORY_CODE_EN "Factory"
+#define RSC_OVERCLOCK_CODE_EN "Overclock"
+#define RSC_OC_BINS_COMM_CODE_EN " OC_BINS [0:disabled ... 7:unlimited] "
#define RSC_PERFORMANCE_CODE_EN "Performance"
#define RSC_TARGET_CODE_EN "Target"
#define RSC_LEVEL_CODE_EN "Level"
@@ -1241,6 +1243,12 @@
#define RSC_TECHNOLOGIES_R2H_CODE_EN "Race To Halt Optimization"
#define RSC_TECHNOLOGIES_HYPERV_CODE_EN "Hypervisor"
#define RSC_TECHNOLOGIES_WDT_CODE_EN "Watchdog Timer"
+#define RSC_TECHNOLOGIES_VMD_CODE_EN "Volume Management Device"
+#define RSC_TECHNOLOGIES_GNA_CODE_EN "Gaussian & Neural Accelerator"
+#define RSC_TECHNOLOGIES_HDCP_CODE_EN "Digital Content Protection"
+#define RSC_TECHNOLOGIES_IPU_CODE_EN "Image Processing Unit"
+#define RSC_TECHNOLOGIES_VPU_CODE_EN "Vision Processing Unit"
+#define RSC_TECHNOLOGIES_OC_CODE_EN "Overclocking"
#define RSC_TECH_AMD_CPB_COMM_CODE_EN " Hardware Configuration::CpbDis "
#define RSC_TECH_INTEL_EEO_COMM_CODE_EN " Skylake::Power Control::EEO_Disable "
@@ -1253,6 +1261,8 @@
#define RSC_TECH_INTEL_VMX_COMM_CODE_EN " Intel Virtual Machine Extensions "
#define RSC_TECH_INTEL_VTD_COMM_CODE_EN " I/O MMU virtualization (Intel VT-d) "
#define RSC_TECH_AMD_V_COMM_CODE_EN " I/O MMU virtualization (AMD-Vi) "
+#define RSC_TECH_HDCP_COMM_CODE_EN " High-Bandwidth Digital Content Protection "
+#define RSC_TECH_OC_COMM_CODE_EN " If OC_ENABLED then MSR FLEX_RATIO.OC_BINS "
#define RSC_PERF_MON_TITLE_CODE_EN " Performance Monitoring "
#define RSC_PERF_CAPS_TITLE_CODE_EN " Performance Capabilities "
@@ -2327,11 +2337,12 @@
#define RSC_PPIN_CODE "PPIN#"
#define RSC_PSTATE_CODE "P-State"
#define RSC_UNCORE_CODE "Uncore"
-#define RSC_BOOST_CODE "Turbo Boost"
+#define RSC_BOOST_CODE "Boost"
#define RSC_TURBO_CODE "Turbo"
#define RSC_CPPC_CODE "CPPC"
#define RSC_MAX_CODE "Max"
#define RSC_MIN_CODE "Min"
+#define RSC_BIN_CODE "Bin"
#define RSC_UCLK_CODE "CLK"
#define RSC_MCLK_CODE "MEM"
#define RSC_TGT_CODE "TGT"
diff --git a/x86_64/corefreq-cli-rsc-fr.h b/x86_64/corefreq-cli-rsc-fr.h
index 3f30416..bc236e3 100644
--- a/x86_64/corefreq-cli-rsc-fr.h
+++ b/x86_64/corefreq-cli-rsc-fr.h
@@ -357,6 +357,10 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
#define RSC_FREQUENCY_CODE_FR "Fr""\xa9""quence"
#define RSC_RATIO_CODE_FR "Ratio"
#define RSC_FACTORY_CODE_FR "Usine"
+#define RSC_OVERCLOCK_CODE_FR "Overclock"
+#define RSC_OC_BINS_COMM_CODE_FR \
+ " OC_BINS [0:d""\xa9""sactiv""\xa9"" ... 7:illimit""\xa9""] "
+
#define RSC_PERFORMANCE_CODE_FR "Performance"
#define RSC_TARGET_CODE_FR "Cible"
#define RSC_LEVEL_CODE_FR "Niveau"
@@ -715,6 +719,18 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
#define RSC_TECHNOLOGIES_R2H_CODE_FR "Optimisation Race To Halt"
#define RSC_TECHNOLOGIES_HYPERV_CODE_FR "Hyperviseur"
#define RSC_TECHNOLOGIES_WDT_CODE_FR "Compteur Watchdog"
+#define RSC_TECHNOLOGIES_VMD_CODE_FR \
+ "P""\xa9""riph""\xa9""rique de gestion de volume"
+
+#define RSC_TECHNOLOGIES_GNA_CODE_FR \
+ "Acc""\xa9""l""\xa9""rateur Gaussien & Neuronal"
+
+#define RSC_TECHNOLOGIES_HDCP_CODE_FR \
+ "Protection des contenus num""\xa9""riques"
+
+#define RSC_TECHNOLOGIES_IPU_CODE_FR "Unit""\xa9"" de traitement d'images"
+#define RSC_TECHNOLOGIES_VPU_CODE_FR "Unit""\xa9"" de traitement visuel"
+#define RSC_TECHNOLOGIES_OC_CODE_FR "Surcaden""\xa7""age"
#define RSC_TECH_AMD_CPB_COMM_CODE_FR RSC_TECH_AMD_CPB_COMM_CODE_EN
#define RSC_TECH_INTEL_EEO_COMM_CODE_FR RSC_TECH_INTEL_EEO_COMM_CODE_EN
@@ -727,6 +743,8 @@ do echo -en "$h$l\t""\xc3""\x$h$l""\t"; done; done;echo
#define RSC_TECH_AMD_SVM_COMM_CODE_FR RSC_TECH_AMD_SVM_COMM_CODE_EN
#define RSC_TECH_INTEL_VTD_COMM_CODE_FR RSC_TECH_INTEL_VTD_COMM_CODE_EN
#define RSC_TECH_AMD_V_COMM_CODE_FR RSC_TECH_AMD_V_COMM_CODE_EN
+#define RSC_TECH_HDCP_COMM_CODE_FR RSC_TECH_HDCP_COMM_CODE_EN
+#define RSC_TECH_OC_COMM_CODE_FR " Si OC_ENABLED alors MSR FLEX_RATIO.OC_BINS "
#define RSC_PERF_MON_TITLE_CODE_FR " Gestion de la performance "
#define RSC_PERF_CAPS_TITLE_CODE_FR " Capacit""\xa9""s de performances "
diff --git a/x86_64/corefreq-cli-rsc.c b/x86_64/corefreq-cli-rsc.c
index 9eb95a2..07a0e78 100644
--- a/x86_64/corefreq-cli-rsc.c
+++ b/x86_64/corefreq-cli-rsc.c
@@ -553,6 +553,8 @@ RESOURCE_ST Resource[] = {
LDT(RSC_FREQUENCY),
LDT(RSC_RATIO),
LDT(RSC_FACTORY),
+ LDT(RSC_OVERCLOCK),
+ LDT(RSC_OC_BINS_COMM),
LDT(RSC_PERFORMANCE),
LDT(RSC_TARGET),
LDT(RSC_LEVEL),
@@ -581,6 +583,7 @@ RESOURCE_ST Resource[] = {
LDQ(RSC_CPPC),
LDQ(RSC_MAX),
LDQ(RSC_MIN),
+ LDQ(RSC_BIN),
LDQ(RSC_UCLK),
LDQ(RSC_MCLK),
LDQ(RSC_TGT),
@@ -1151,6 +1154,14 @@ RESOURCE_ST Resource[] = {
LDQ(RSC_TECH_HYPERV_KBOX),
LDQ(RSC_TECH_HYPERV_VMWARE),
LDQ(RSC_TECH_HYPERV_HYPERV),
+ LDT(RSC_TECHNOLOGIES_VMD),
+ LDT(RSC_TECHNOLOGIES_GNA),
+ LDT(RSC_TECHNOLOGIES_HDCP),
+ LDT(RSC_TECH_HDCP_COMM),
+ LDT(RSC_TECHNOLOGIES_IPU),
+ LDT(RSC_TECHNOLOGIES_VPU),
+ LDT(RSC_TECHNOLOGIES_OC),
+ LDT(RSC_TECH_OC_COMM),
LDT(RSC_PERF_MON_TITLE),
LDT(RSC_PERF_CAPS_TITLE),
LDT(RSC_VERSION),
diff --git a/x86_64/corefreq-cli-rsc.h b/x86_64/corefreq-cli-rsc.h
index f3fb00a..7a8efc1 100644
--- a/x86_64/corefreq-cli-rsc.h
+++ b/x86_64/corefreq-cli-rsc.h
@@ -356,6 +356,8 @@ enum {
RSC_FREQUENCY,
RSC_RATIO,
RSC_FACTORY,
+ RSC_OVERCLOCK,
+ RSC_OC_BINS_COMM,
RSC_PERFORMANCE,
RSC_TARGET,
RSC_LEVEL,
@@ -384,6 +386,7 @@ enum {
RSC_CPPC,
RSC_MAX,
RSC_MIN,
+ RSC_BIN,
RSC_UCLK,
RSC_MCLK,
RSC_TGT,
@@ -954,6 +957,14 @@ enum {
RSC_TECH_HYPERV_KBOX,
RSC_TECH_HYPERV_VMWARE,
RSC_TECH_HYPERV_HYPERV,
+ RSC_TECHNOLOGIES_VMD,
+ RSC_TECHNOLOGIES_GNA,
+ RSC_TECHNOLOGIES_HDCP,
+ RSC_TECH_HDCP_COMM,
+ RSC_TECHNOLOGIES_IPU,
+ RSC_TECHNOLOGIES_VPU,
+ RSC_TECHNOLOGIES_OC,
+ RSC_TECH_OC_COMM,
RSC_PERF_MON_TITLE,
RSC_PERF_CAPS_TITLE,
RSC_VERSION,
diff --git a/x86_64/corefreq-cli.c b/x86_64/corefreq-cli.c
index 626b090..a8d0464 100644
--- a/x86_64/corefreq-cli.c
+++ b/x86_64/corefreq-cli.c
@@ -216,12 +216,33 @@ void AggregateRatio(void)
}
InsertionSortRuler(Ruler.Uniq, Ruler.Count, BOOST(MIN));
+ #ifndef UI_RULER_MINIMUM
Ruler.Minimum = (double) lowest;
+ #elif (UI_RULER_MINIMUM > 0) && (UI_RULER_MINIMUM <= MAX_WIDTH)
+ Ruler.Minimum = (double) UI_RULER_MINIMUM;
+ #else
+ Ruler.Minimum = 1.0;
+ #endif
+ #ifndef UI_RULER_MAXIMUM
Ruler.Maximum = (double) highest;
- Ruler.Median = (double) RO(Shm)->Cpu[
- Ruler.Top[BOOST(ACT)]
- ].Boost[BOOST(ACT)];
+ #elif (UI_RULER_MAXIMUM > 0) && (UI_RULER_MAXIMUM <= MAX_WIDTH)
+ Ruler.Maximum = (double) UI_RULER_MAXIMUM;
+ #else
+ Ruler.Maximum = (double) MIN_WIDTH;
+ #endif
+ #if !defined(UI_RULER_MINIMUM) && !defined(UI_RULER_MAXIMUM)
+ {
+ const double median = (double) RO(Shm)->Cpu[
+ Ruler.Top[BOOST(ACT)]
+ ].Boost[BOOST(ACT)];
+ if ((median > Ruler.Minimum) && (median < Ruler.Maximum)) {
+ Ruler.Median = median;
+ }
+ }
+ #else
+ Ruler.Median = 0.0;
+ #endif
if (Ruler.Median == 0.0) {
Ruler.Median = (Ruler.Minimum + Ruler.Maximum) / 2.0;
}
@@ -1349,10 +1370,23 @@ REASON_CODE SysInfoProc(Window *win,
23, hSpace, RO(Shm)->Proc.Features.Factory.Ratio ),
RefreshFactoryFreq );
+ if (RO(Shm)->Proc.Features.OC_Enable)
+ {
+ PUT( SCANKEY_NULL, attrib[!RO(Shm)->Proc.Features.OC_Lock],
+ width, 2, "%s%.*s[%7.*s]", RSC(OVERCLOCK).CODE(),
+ width - 12 - RSZ(OVERCLOCK), hSpace, 6,
+ RO(Shm)->Proc.Features.OC_Lock ?
+ RSC(LOCK).CODE() : RSC(UNLOCK).CODE() );
+
+ GridHover( PUT( SCANKEY_NULL, attrib[3], width, 0,
+ "%.*s""%s""%.*s""%+5d""%.*s""[%+4d ]",
+ 17, hSpace, RSC(BIN).CODE(),
+ 2, hSpace, RO(Shm)->Proc.Features.Factory.Overclock,
+ 23, hSpace, RO(Shm)->Proc.Features.Factory.Bins ),
+ (char *) RSC(OC_BINS_COMM).CODE() );
+ }
PUT(SCANKEY_NULL, attrib[0], width, 2, "%s", RSC(PERFORMANCE).CODE());
- PUT(SCANKEY_NULL, attrib[0], width, 3, "%s", RSC(PSTATE).CODE());
-
coreClock = (CLOCK_ARG) {.NC = 0, .Offset = 0};
coreClock.NC = BOXKEY_RATIO_CLOCK_OR | CLOCK_MOD_TGT;
@@ -1436,15 +1470,17 @@ REASON_CODE SysInfoProc(Window *win,
width, OutFunc, cellPadding, attrib[3] ),
RefreshTopFreq, BOOST(HWP_TGT) );
}
- PUT( SCANKEY_NULL, attrib[RO(Shm)->Proc.Features.Turbo_Unlock],
- width, 2, "%s%.*s[%7.*s]", RSC(BOOST).CODE(),
- width - 12 - RSZ(BOOST), hSpace, 6,
- RO(Shm)->Proc.Features.Turbo_Unlock ?
- RSC(UNLOCK).CODE() : RSC(LOCK).CODE() );
-
if ((RO(Shm)->Proc.Features.Info.Vendor.CRC == CRC_AMD)
|| (RO(Shm)->Proc.Features.Info.Vendor.CRC == CRC_HYGON))
{
+ if (RO(Shm)->Proc.Technology.Turbo == 1)
+ {
+ PUT( SCANKEY_NULL, attrib[RO(Shm)->Proc.Features.Turbo_Unlock],
+ width, 3, "%s%.*s[%7.*s]", RSC(BOOST).CODE(),
+ width - (OutFunc == NULL ? 15 : 13) - RSZ(BOOST), hSpace, 6,
+ RO(Shm)->Proc.Features.Turbo_Unlock ?
+ RSC(UNLOCK).CODE() : RSC(LOCK).CODE() );
+ }
if (RO(Shm)->Proc.Features.XtraCOF >= 2)
{
CFlop = &RO(Shm)->Cpu[
@@ -1479,8 +1515,15 @@ REASON_CODE SysInfoProc(Window *win,
width, OutFunc, cellPadding, attrib[3] ),
RefreshTopFreq, BOOST(CPB) );
}
+ PUT(SCANKEY_NULL, attrib[0], width, 3, "%s", RSC(PSTATE).CODE());
+ } else {
+ PUT( SCANKEY_NULL, attrib[RO(Shm)->Proc.Features.Turbo_Unlock],
+ width, 2, "%s %s%.*s[%7.*s]",
+ RSC(TURBO).CODE(), RSC(BOOST).CODE(),
+ width - 13 - RSZ(TURBO) - RSZ(BOOST), hSpace, 6,
+ RO(Shm)->Proc.Features.Turbo_Unlock ?
+ RSC(UNLOCK).CODE() : RSC(LOCK).CODE() );
}
-
for(boost = BOOST(1C), activeCores = 1;
boost > BOOST(1C)-(enum RATIO_BOOST)RO(Shm)->Proc.Features.SpecTurboRatio;
boost--, activeCores++)
@@ -1491,8 +1534,13 @@ REASON_CODE SysInfoProc(Window *win,
RO(Shm)->Proc.Service.Core : Ruler.Top[boost];
char pfx[10+1+1];
+ if ((RO(Shm)->Proc.Features.Info.Vendor.CRC == CRC_AMD)
+ || (RO(Shm)->Proc.Features.Info.Vendor.CRC == CRC_HYGON))
+ {
+ StrFormat(pfx, 10+1+1, "P%-2u", activeCores);
+ } else {
StrFormat(pfx, 10+1+1, "%2uC", activeCores);
-
+ }
CFlop = &RO(Shm)->Cpu[primary].FlipFlop[!RO(Shm)->Cpu[primary].Toggle];
GridCall( PrintRatioFreq(win, CFlop,
@@ -4389,6 +4437,66 @@ REASON_CODE SysInfoTech(Window *win,
: (char*) RSC(NOT_AVAILABLE).CODE(),
SCANKEY_NULL,
NULL
+ },
+ {
+ (unsigned int[]) { CRC_INTEL, 0 },
+ RO(Shm)->Proc.Technology.VMD == 1,
+ 2, "%s%.*sVMD [%3s]",
+ RSC(TECHNOLOGIES_VMD).CODE(), NULL,
+ width - 14 - RSZ(TECHNOLOGIES_VMD),
+ NULL,
+ SCANKEY_NULL,
+ NULL
+ },
+ {
+ (unsigned int[]) { CRC_INTEL, 0 },
+ RO(Shm)->Proc.Technology.GNA == 1,
+ 2, "%s%.*sGNA [%3s]",
+ RSC(TECHNOLOGIES_GNA).CODE(), NULL,
+ width - 14 - RSZ(TECHNOLOGIES_GNA),
+ NULL,
+ SCANKEY_NULL,
+ NULL
+ },
+ {
+ (unsigned int[]) { CRC_INTEL, 0 },
+ RO(Shm)->Proc.Technology.HDCP == 1,
+ 2, "%s%.*sHDCP [%3s]",
+ RSC(TECHNOLOGIES_HDCP).CODE(), RSC(TECH_HDCP_COMM).CODE(),
+ width - 15 - RSZ(TECHNOLOGIES_HDCP),
+ NULL,
+ SCANKEY_NULL,
+ NULL
+ },
+ {
+ (unsigned int[]) { CRC_INTEL, 0 },
+ RO(Shm)->Proc.Technology.IPU == 1,
+ 2, "%s%.*sIPU [%3s]",
+ RSC(TECHNOLOGIES_IPU).CODE(), NULL,
+ width - 14 - RSZ(TECHNOLOGIES_IPU),
+ NULL,
+ SCANKEY_NULL,
+ NULL
+ },
+ {
+ (unsigned int[]) { CRC_INTEL, 0 },
+ RO(Shm)->Proc.Technology.VPU == 1,
+ 2, "%s%.*sVPU [%3s]",
+ RSC(TECHNOLOGIES_VPU).CODE(), NULL,
+ width - 14 - RSZ(TECHNOLOGIES_VPU),
+ NULL,
+ SCANKEY_NULL,
+ NULL
+ },
+ {
+ (unsigned int[]) { CRC_INTEL, 0 },
+ RO(Shm)->Proc.Technology.OC == 1,
+ 2, "%s%.*sOC [%3s]",
+ RSC(TECHNOLOGIES_OC).CODE(), RSC(TECH_OC_COMM).CODE(),
+ width - 13 - RSZ(TECHNOLOGIES_OC),
+ NULL,
+ SCANKEY_NULL,
+ NULL
}
};
size_t idx;
@@ -17651,8 +17759,10 @@ void Layout_Ruler_Load(Layer *layer, CUINT row)
/* Alternate the color of the frequency ratios */
while (idx--)
- {
- double fPos = (Ruler.Uniq[idx] * Draw.Area.LoadWidth) / Ruler.Maximum;
+ if (Ruler.Uniq[idx] <= Ruler.Maximum)
+ {
+ const double fPos = (Ruler.Uniq[idx] * Draw.Area.LoadWidth)
+ / Ruler.Maximum;
CUINT hPos = (CUINT) fPos;
ASCII tabStop[10+1] = "00";
@@ -17669,7 +17779,7 @@ void Layout_Ruler_Load(Layer *layer, CUINT row)
bright = !bright;
}
lPos = hPos >= margin ? hPos - margin : margin;
- }
+ }
LayerCopyAt(layer, hLoad1.origin.col, hLoad1.origin.row, hLoad1.length,
hLoad1.attr[Draw.Load], hLoad1.code[Draw.Load]);
}
diff --git a/x86_64/corefreq-ui.c b/x86_64/corefreq-ui.c
index 34e40c0..0d67fc4 100644
--- a/x86_64/corefreq-ui.c
+++ b/x86_64/corefreq-ui.c
@@ -608,13 +608,21 @@ int GetKey(SCANKEY *scan, struct timespec *tsec)
SCREEN_SIZE GetScreenSize(void)
{
- SCREEN_SIZE _screenSize = {.width = 0, .height = 0};
- struct winsize ts;
+ SCREEN_SIZE _screenSize = {.width = MIN_WIDTH, .height = MIN_HEIGHT};
- ioctl(STDIN_FILENO, TIOCGWINSZ, &ts);
- _screenSize.width = (int) ts.ws_col;
- _screenSize.height = (int) ts.ws_row;
+#if defined(TIOCGWINSZ)
+ struct winsize ts;
+ if (ioctl(STDIN_FILENO, TIOCGWINSZ, &ts) >= 0) {
+ const int _col = (int) ts.ws_col, _row = (int) ts.ws_row;
+ if (_col > 0) {
+ _screenSize.width = _col;
+ }
+ if (_row > 0) {
+ _screenSize.height = _row;
+ }
+ }
+#endif
return _screenSize;
}
diff --git a/x86_64/corefreq-ui.h b/x86_64/corefreq-ui.h
index 0cc91e6..91dac2a 100644
--- a/